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x86: fix XIP SOC support and defaults

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XIP support in x86 was something of a mess. This
patch does the following:

- Generic ia32 SOC no longer defines a "flash" region
  as generic X86 devices don't have a microcontroller-
  like concept of flash. The same has been done for apollo_lake.
- Generic ia32 and apollo_lake SOCs starts memory at 1MB.
- Generic ia32 SOC may optionally have CONFIG_XIP enabled.
  The board definition must provide a flash region definition
  that gets exposed as DT_PHYS_LOAD_ADDR.
- Fixed definitions for RAM/ROM source addresses in ia32's
  linker.ld when XIP is turned off.
- Support for enabling XIP on apollo_lake SOC removed, there's
  no use-case.
- acrn and gpmrb boards have flash and XIP related definitions
  removed.
- qemu_x86 has a fake flash region added, immediately after system
  RAM, for use when XIP is enabled. This used to be in the ia32 SOC.
  However, the default for qemu_x86 is to now have XIP disabled.
- Fixed tests/kernel/xip to run by default on boards that enable
  XIP by default, plus an additional test to exercise XIP on
  qemu_x86 (which supports it but has XIP switched off by default)

The overall effect of this patch is to:

- Remove XIP configuration for SOC/boards where it does not make
  any sense to have it
- Support testing XIP on qemu_x86 via tests/kernel/xip, but leave
  it off by default for other tests, to ensure it doesn't bit-rot
  and that the system works in both scenarios.
- XIP remains an available feature for boards that need it.

Fixes: #18956

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2019-09-10 00:41:08 -07:00 • committed by Anas Nashif
commit 9df9994572
14 changed files with 32 additions and 62 deletions
Download patch file Download diff file Expand all files Collapse all files

10
boards/x86/acrn/acrn.dts
View file

@ -8,7 +8,6 @@
#include <mem.h>
#define DT_FLASH_SIZE DT_SIZE_K(8192)
#define DT_SRAM_SIZE DT_SIZE_K(8192)
#include <ia32.dtsi>
@ -24,7 +23,6 @@
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
@ -39,11 +37,3 @@
status = "okay";
current-speed = <115200>;
};
&flash0 {
reg = <0x100000 DT_FLASH_SIZE>;
};
&sram0 {
reg = <0x400000 DT_SRAM_SIZE>;
};

2
boards/x86/acrn/acrn.yaml
View file

@ -5,4 +5,4 @@ arch: x86
toolchain:
- zephyr
ram: 8192
flash: 8192

1
boards/x86/acrn/acrn_defconfig
View file

@ -10,6 +10,5 @@ CONFIG_SERIAL=y
CONFIG_UART_NS16550=y
CONFIG_UART_CONSOLE=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000
CONFIG_XIP=n
CONFIG_BUILD_OUTPUT_BIN=y
CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n

2
boards/x86/gpmrb/gpmrb.dts
View file

@ -8,7 +8,6 @@
#include <mem.h>
#define DT_FLASH_SIZE DT_SIZE_K(8912)
#define DT_SRAM_SIZE DT_SIZE_M(2048)
#include <apollo_lake.dtsi>
@ -19,7 +18,6 @@
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart2;
zephyr,shell-uart = &uart2;
zephyr,bt-uart = &uart1;

6
boards/x86/qemu_x86/Kconfig.board
View file

@ -1,9 +1,4 @@
# SPDX-License-Identifier: Apache-2.0
#
# The QEMU targets themselves are not XIP, everything is actually RAM, but we
# pretend the first 4 megabytes are a memory-mapped flash region. This is done
# to ensure that the XIP data copying infrastructure doesn't bit-rot on
# x86.
config BOARD_QEMU_X86
bool "QEMU x86"
@ -12,4 +7,3 @@ config BOARD_QEMU_X86
select HAS_DTS_ETHERNET
select CPU_HAS_FPU
select HAS_COVERAGE_SUPPORT
select XIP

7
boards/x86/qemu_x86/qemu_x86.dts
View file

@ -4,8 +4,8 @@
#include <mem.h>
#define DT_FLASH_SIZE DT_SIZE_K(4096)
#define DT_SRAM_SIZE DT_SIZE_K(4096)
#define DT_FLASH_SIZE DT_SIZE_K(4096)
#include <ia32.dtsi>
@ -13,6 +13,11 @@
model = "QEMU X86";
compatible = "intel,ia32";
flash0: flash@500000 {
compatible = "soc-nv-flash";
reg = <0x00500000 DT_FLASH_SIZE>;
};
aliases {
uart-0 = &uart0;
uart-1 = &uart1;

1
boards/x86/qemu_x86/qemu_x86_coverage_defconfig
View file

@ -14,7 +14,6 @@ CONFIG_UART_NS16550=y
CONFIG_UART_CONSOLE=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000
CONFIG_TEST_RANDOM_GENERATOR=y
CONFIG_XIP=y
CONFIG_X86_MMU=y
CONFIG_X86_MMU_PAGE_POOL_PAGES=15
CONFIG_DEBUG_INFO=y

2
boards/x86/up_squared/up_squared.dts
View file

@ -8,7 +8,6 @@
#include <mem.h>
#define DT_FLASH_SIZE DT_SIZE_K(8912)
#define DT_SRAM_SIZE DT_SIZE_M(2048)
#include <apollo_lake.dtsi>
@ -19,7 +18,6 @@
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,bt-uart = &uart1;

9
dts/x86/apollo_lake.dtsi
View file

@ -22,15 +22,10 @@
};
flash0: flash@100000{
compatible = "soc-nv-flash";
reg = <0x00100000 DT_FLASH_SIZE>;
};
sram0: memory@400000 {
sram0: memory@100000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x00400000 DT_SRAM_SIZE>;
reg = <0x00100000 DT_SRAM_SIZE>;
};
intc: ioapic@fec00000 {

10
dts/x86/ia32.dtsi
View file

@ -27,16 +27,10 @@
#interrupt-cells = <3>;
};
flash0: flash@100000 {
compatible = "soc-nv-flash";
reg = <0x00100000 DT_FLASH_SIZE>;
};
sram0: memory@500000 {
sram0: memory@100000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x00500000 DT_SRAM_SIZE>;
reg = <0x00100000 DT_SRAM_SIZE>;
};
soc {

17
soc/x86/apollo_lake/linker.ld
View file

@ -6,24 +6,13 @@
#include <autoconf.h>
#include <generated_dts_board.h>
/* physical address where the kernel is loaded */
#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR
/* physical address of RAM */
#ifdef CONFIG_XIP
#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
#else /* !CONFIG_XIP */
#define PHYS_RAM_ADDR PHYS_LOAD_ADDR
#endif /* CONFIG_XIP */
#define PHYS_LOAD_ADDR DT_PHYS_RAM_ADDR
#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
MEMORY
{
#ifdef CONFIG_XIP
ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K
RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
#else /* !CONFIG_XIP */
RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_RAM_SIZE*1K
#endif /* CONFIG_XIP */
RAM (wx) : ORIGIN = DT_PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
/*
* It doesn't matter where this region goes as it is stripped from the

15
soc/x86/ia32/linker.ld
View file

@ -9,28 +9,31 @@
* @brief Linker command/script file
*
* This is the linker script for both standard images and XIP images.
*
* If XIP is turned on, board-level DTS must specify a flash region
* that doesn't overlap with sram0, so that DT_PHYS_LOAD_ADDR is set.
*/
#include <autoconf.h>
#include <generated_dts_board.h>
/* physical address where the kernel is loaded */
#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR
/* physical address of RAM */
#ifdef CONFIG_XIP
#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR
#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
#else /* !CONFIG_XIP */
#define PHYS_RAM_ADDR PHYS_LOAD_ADDR
#define PHYS_LOAD_ADDR DT_PHYS_RAM_ADDR
#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
#endif /* CONFIG_XIP */
MEMORY
{
#ifdef CONFIG_XIP
ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K
RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
#else /* !CONFIG_XIP */
RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_RAM_SIZE*1K
RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
#endif /* CONFIG_XIP */
/*

1
tests/kernel/xip/prj.conf
View file

@ -1,2 +1 @@
CONFIG_XIP=y
CONFIG_ZTEST=y

11
tests/kernel/xip/testcase.yaml
View file

@ -1,5 +1,12 @@
tests:
arch.common.xip:
arch_exclude: xtensa
platform_exclude: cc3220sf_launchxl minnowboard
filter: CONFIG_XIP
tags: xip
# Platforms where XIP is supported but not on by default (rare, typically
# emulator targets, to show that XIP is working for a particular arch)
arch.common.xip.nondefault:
platform_whitelist: qemu_x86 qemu_x86_coverage
extra_configs:
- CONFIG_XIP=y
tags: xip