x86: fix XIP SOC support and defaults
XIP support in x86 was something of a mess. This patch does the following: - Generic ia32 SOC no longer defines a "flash" region as generic X86 devices don't have a microcontroller- like concept of flash. The same has been done for apollo_lake. - Generic ia32 and apollo_lake SOCs starts memory at 1MB. - Generic ia32 SOC may optionally have CONFIG_XIP enabled. The board definition must provide a flash region definition that gets exposed as DT_PHYS_LOAD_ADDR. - Fixed definitions for RAM/ROM source addresses in ia32's linker.ld when XIP is turned off. - Support for enabling XIP on apollo_lake SOC removed, there's no use-case. - acrn and gpmrb boards have flash and XIP related definitions removed. - qemu_x86 has a fake flash region added, immediately after system RAM, for use when XIP is enabled. This used to be in the ia32 SOC. However, the default for qemu_x86 is to now have XIP disabled. - Fixed tests/kernel/xip to run by default on boards that enable XIP by default, plus an additional test to exercise XIP on qemu_x86 (which supports it but has XIP switched off by default) The overall effect of this patch is to: - Remove XIP configuration for SOC/boards where it does not make any sense to have it - Support testing XIP on qemu_x86 via tests/kernel/xip, but leave it off by default for other tests, to ensure it doesn't bit-rot and that the system works in both scenarios. - XIP remains an available feature for boards that need it. Fixes: #18956 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
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parent
702325ddb2
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9df9994572
14 changed files with 32 additions and 62 deletions
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@ -8,7 +8,6 @@
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#include <mem.h>
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#define DT_FLASH_SIZE DT_SIZE_K(8192)
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#define DT_SRAM_SIZE DT_SIZE_K(8192)
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#include <ia32.dtsi>
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@ -24,7 +23,6 @@
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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};
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@ -39,11 +37,3 @@
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status = "okay";
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current-speed = <115200>;
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};
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&flash0 {
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reg = <0x100000 DT_FLASH_SIZE>;
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};
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&sram0 {
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reg = <0x400000 DT_SRAM_SIZE>;
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};
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@ -5,4 +5,4 @@ arch: x86
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toolchain:
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- zephyr
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ram: 8192
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flash: 8192
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@ -10,6 +10,5 @@ CONFIG_SERIAL=y
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CONFIG_UART_NS16550=y
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CONFIG_UART_CONSOLE=y
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000
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CONFIG_XIP=n
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CONFIG_BUILD_OUTPUT_BIN=y
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CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n
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@ -8,7 +8,6 @@
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#include <mem.h>
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#define DT_FLASH_SIZE DT_SIZE_K(8912)
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#define DT_SRAM_SIZE DT_SIZE_M(2048)
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#include <apollo_lake.dtsi>
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@ -19,7 +18,6 @@
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,console = &uart2;
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zephyr,shell-uart = &uart2;
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zephyr,bt-uart = &uart1;
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@ -1,9 +1,4 @@
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# SPDX-License-Identifier: Apache-2.0
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#
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# The QEMU targets themselves are not XIP, everything is actually RAM, but we
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# pretend the first 4 megabytes are a memory-mapped flash region. This is done
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# to ensure that the XIP data copying infrastructure doesn't bit-rot on
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# x86.
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config BOARD_QEMU_X86
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bool "QEMU x86"
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@ -12,4 +7,3 @@ config BOARD_QEMU_X86
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select HAS_DTS_ETHERNET
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select CPU_HAS_FPU
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select HAS_COVERAGE_SUPPORT
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select XIP
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@ -4,8 +4,8 @@
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#include <mem.h>
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#define DT_FLASH_SIZE DT_SIZE_K(4096)
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#define DT_SRAM_SIZE DT_SIZE_K(4096)
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#define DT_FLASH_SIZE DT_SIZE_K(4096)
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#include <ia32.dtsi>
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@ -13,6 +13,11 @@
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model = "QEMU X86";
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compatible = "intel,ia32";
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flash0: flash@500000 {
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compatible = "soc-nv-flash";
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reg = <0x00500000 DT_FLASH_SIZE>;
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};
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aliases {
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uart-0 = &uart0;
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uart-1 = &uart1;
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@ -14,7 +14,6 @@ CONFIG_UART_NS16550=y
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CONFIG_UART_CONSOLE=y
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000
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CONFIG_TEST_RANDOM_GENERATOR=y
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CONFIG_XIP=y
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CONFIG_X86_MMU=y
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CONFIG_X86_MMU_PAGE_POOL_PAGES=15
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CONFIG_DEBUG_INFO=y
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@ -8,7 +8,6 @@
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#include <mem.h>
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#define DT_FLASH_SIZE DT_SIZE_K(8912)
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#define DT_SRAM_SIZE DT_SIZE_M(2048)
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#include <apollo_lake.dtsi>
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,bt-uart = &uart1;
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@ -22,15 +22,10 @@
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};
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flash0: flash@100000{
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compatible = "soc-nv-flash";
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reg = <0x00100000 DT_FLASH_SIZE>;
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};
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sram0: memory@400000 {
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sram0: memory@100000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x00400000 DT_SRAM_SIZE>;
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reg = <0x00100000 DT_SRAM_SIZE>;
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};
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intc: ioapic@fec00000 {
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@ -27,16 +27,10 @@
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#interrupt-cells = <3>;
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};
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flash0: flash@100000 {
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compatible = "soc-nv-flash";
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reg = <0x00100000 DT_FLASH_SIZE>;
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};
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sram0: memory@500000 {
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sram0: memory@100000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x00500000 DT_SRAM_SIZE>;
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reg = <0x00100000 DT_SRAM_SIZE>;
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};
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soc {
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@ -6,24 +6,13 @@
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#include <autoconf.h>
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#include <generated_dts_board.h>
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/* physical address where the kernel is loaded */
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#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR
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/* physical address of RAM */
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#ifdef CONFIG_XIP
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#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
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#else /* !CONFIG_XIP */
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#define PHYS_RAM_ADDR PHYS_LOAD_ADDR
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#endif /* CONFIG_XIP */
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#define PHYS_LOAD_ADDR DT_PHYS_RAM_ADDR
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#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
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MEMORY
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{
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#ifdef CONFIG_XIP
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ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K
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RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
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#else /* !CONFIG_XIP */
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RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_RAM_SIZE*1K
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#endif /* CONFIG_XIP */
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RAM (wx) : ORIGIN = DT_PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
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/*
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* It doesn't matter where this region goes as it is stripped from the
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* @brief Linker command/script file
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*
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* This is the linker script for both standard images and XIP images.
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*
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* If XIP is turned on, board-level DTS must specify a flash region
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* that doesn't overlap with sram0, so that DT_PHYS_LOAD_ADDR is set.
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*/
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#include <autoconf.h>
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#include <generated_dts_board.h>
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/* physical address where the kernel is loaded */
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#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR
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/* physical address of RAM */
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#ifdef CONFIG_XIP
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#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
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#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR
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#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
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#else /* !CONFIG_XIP */
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#define PHYS_RAM_ADDR PHYS_LOAD_ADDR
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#define PHYS_LOAD_ADDR DT_PHYS_RAM_ADDR
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#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
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#endif /* CONFIG_XIP */
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MEMORY
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{
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#ifdef CONFIG_XIP
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ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K
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RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
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RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
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#else /* !CONFIG_XIP */
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RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_RAM_SIZE*1K
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RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
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#endif /* CONFIG_XIP */
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/*
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@ -1,2 +1 @@
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CONFIG_XIP=y
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CONFIG_ZTEST=y
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tests:
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arch.common.xip:
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arch_exclude: xtensa
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platform_exclude: cc3220sf_launchxl minnowboard
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filter: CONFIG_XIP
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tags: xip
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# Platforms where XIP is supported but not on by default (rare, typically
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# emulator targets, to show that XIP is working for a particular arch)
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arch.common.xip.nondefault:
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platform_whitelist: qemu_x86 qemu_x86_coverage
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extra_configs:
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- CONFIG_XIP=y
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tags: xip
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