Drop snprintf() and use snprintk() as snprintk()
is more suitable for the networking code.
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
NET_BUF_ASSERT() tranlates into nothing in presence
of CONFIG_ASSERT=y, which is misleading.
Use __ASSERT() in NET_BUF_ASSERT().
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
PWM driver for LiteX SoC builder was created.
Because LiteX supports only one channel for each PWM device,
an appropriate restriction was made.
Signed-off-by: Robert Winkler <rwinkler@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Fix bug when connecting using whitelist and split controller.
The peer address was set to an all zeroes address.
Bug using shell:
bt init
bt wl-add <addr>
bt wl-connect on
Connected: 00:00:00:00:00:00 (public)
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
In some cases, we've seen the output files be truncated when the
python script has been rebuilt into a .pex before running it --
likely due to buffering.
Closing files explicitly is the right thing to do anyway, so let's
do it.
Signed-off-by: Olof Johansson <olof@lixom.net>
For the native_posix board where hwinfo is not implemented tests were
reporting errors.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
This adds I2C bitbang driver for LiteX SoC builder with its bindings.
Signed-off-by: Robert Winkler <rwinkler@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Fix an issue with 'ZEPHYR_TOOLCHAIN_VARIANT=host' where CMAKE_C_FLAGS
was incorrectly assumed to be set.
This fixes#21614
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
No packet was previously sent, because net_pkt_set_ppp(pkt, true) was
not called on the outgoing packet. Also the received protocol instead of
LCP was used, which was incorrectly interpreted by remote peer.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Received net_pkt is always discarded in ppp_recv() if we return
NET_OK. Don't do this in ppp_fsm_recv_discard_req().
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
When iterating though configuration options it is possible that we will
fail to add data to nack_buf and hence unref it in error handling
path. Just after that we will unref buf, which has nack_buf in its
buffer chain.
Drop code unrefing nack_buf and just go directly to unrefing buf.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
There is no possibility right now that 'nack == NULL' and 'nack_buf !=
NULL', so drop code path for that case.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
The code tried to use the allocated pkt ptr before checking for
NULL value.
Fixes#21699
Coverity-CID: 206608
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Add support for specifying PWM flags for the NXP Kinetis FlexTimer
(FTM) PWM driver through the device tree.
All in-tree clients of this PWM controller are active-low LEDs.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for specifying the PWM signal polarity through flags to
the NXP Kinetis FlexTimer (FTM) PWM driver.
Prior to this change the FTM PWM driver always produced inverted
polarity (active-low) PWM signals.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for requesting an inverted PWM pulse (active-low) when
setting up the period and pulse width of a PWM pin. This is useful
when driving external, active-low circuitry (e.g. an LED) with a PWM
signal.
All in-tree PWM drivers is updated to match the new API signature, but
no driver support for inverted PWM signals is added yet.
All in-tree PWM consumers are updated to pass a flags value of 0
(0 meaning default, which is normal PWM polarity).
Fixes#21384.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The SRAM address and size are currently available as both
DT_SRAM_{BASE_ADDRESS,SIZE} and as CONFIG_SRAM_{BASE_ADDRESS,SIZE} (via
the Kconfig preprocessor).
Use the CONFIG_SRAM_* versions everywhere, and remove generation of the
DT_SRAM_* versions from gen_defines.py.
The Kconfig symbols currently depend on 'ARC || ARM || NIOS2 || X86'.
Not sure why, so I removed it.
It looks like no configuration files set CONFIG_SRAM_* at the moment, so
another option might be to use the DT_* symbols everywhere instead. Some
Kconfig.defconfig.series files add defaults to them though.
Also improve the help texts for CONFIG_SRAM_* to say that they normally
come from devicetree rather than configuration files.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit removes the ignore tags for the tests that work after the
changes in the PR #20267.
In the future, this ignored testing tag list will be further reduced
as critical bugs for the qemu_cortex_r5 platform are addressed
(see #20217).
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU"
cores.
Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within the same project, the RPU and APU should be
considered separate platforms and handled accordingly.
This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol
indicating that Xilinx ZynqMP SoC is used, and adds a new symbol,
SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform.
When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU
symbol should be added and used to conditionally handle APU-specific
code.
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit fixes the following problems with the RPU device tree:
1. The core type of the RPU of ZynqMP SoC is Cortex-R5F, not
Cortex-R4.
2. RPU and APU use different interrupt controllers (PL390 GICv1 and
GIC-400 GICv2, respectively) mapped to the same CPU local bus address
region but with different offsets for the distributor and CPU
interrupt control register sets. The GIC address mapping specified by
the current dts is that of an APU and does not apply to the PL390
GICv1 of an RPU (refer to the "Zynq UltraScale+ Devices Register
Reference" document from Xilinx for more information).
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and
Cortex-A for APU.
Since the current Zephyr architecture cannot support AMP of Cortex-R
and Cortex-A within one project, the RPU and APU should be considered
separate platforms.
This commit relocates the device tree nodes that are not common between
RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi).
When Cortex-A53 APU support is added in the future, an additional dtsi
file (zynqmp_apu.dtsi) for specifying the APU device tree should be
added.
For more details, refer to the issue #20217.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
