soc: arm: xilinx_zynqmp: Refactor for multi-arch support.
The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU" cores. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within the same project, the RPU and APU should be considered separate platforms and handled accordingly. This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol indicating that Xilinx ZynqMP SoC is used, and adds a new symbol, SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform. When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU symbol should be added and used to conditionally handle APU-specific code. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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6 changed files with 22 additions and 6 deletions
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@ -3,4 +3,4 @@
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config BOARD_QEMU_CORTEX_R5
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bool "Cortex-R5 Emulation (QEMU)"
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depends on SOC_XILINX_ZYNQMP
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depends on SOC_XILINX_ZYNQMP_RPU
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@ -1,5 +1,5 @@
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CONFIG_ARM=y
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CONFIG_SOC_XILINX_ZYNQMP=y
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CONFIG_SOC_XILINX_ZYNQMP_RPU=y
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CONFIG_BOARD_QEMU_CORTEX_R5=y
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CONFIG_XIP=n
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5
soc/arm/xilinx_zynqmp/Kconfig
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5
soc/arm/xilinx_zynqmp/Kconfig
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# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
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# SPDX-License-Identifier: Apache-2.0
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config SOC_XILINX_ZYNQMP
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bool
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@ -1,4 +1,5 @@
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# Copyright (c) 2019 Lexmark International, Inc.
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# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
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# SPDX-License-Identifier: Apache-2.0
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if SOC_XILINX_ZYNQMP
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@ -6,6 +7,8 @@ if SOC_XILINX_ZYNQMP
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config SOC
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default "xilinx_zynqmp"
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if SOC_XILINX_ZYNQMP_RPU
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config NUM_IRQS
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# must be >= the highest interrupt number used
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# - include the UART interrupts
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@ -23,6 +26,8 @@ config NUM_2ND_LEVEL_AGGREGATORS
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 12000000
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endif # SOC_XILINX_ZYNQMP_RPU
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# Workaround for not being able to have commas in macro arguments
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DT_CHOSEN_Z_FLASH := zephyr,flash
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@ -32,4 +37,4 @@ config FLASH_SIZE
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config FLASH_BASE_ADDRESS
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
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endif
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endif # SOC_XILINX_ZYNQMP
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@ -1,9 +1,11 @@
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# Copyright (c) 2019 Lexmark International, Inc.
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# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
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# SPDX-License-Identifier: Apache-2.0
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config SOC_XILINX_ZYNQMP
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bool "Xilinx ZynqMP"
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config SOC_XILINX_ZYNQMP_RPU
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bool "Xilinx ZynqMP RPU"
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select CPU_CORTEX_R5
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select SOC_XILINX_ZYNQMP
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select GIC_V1
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select MULTI_LEVEL_INTERRUPTS
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select 2ND_LEVEL_INTERRUPTS
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@ -1,8 +1,12 @@
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/*
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* Copyright (c) 2019 Lexmark International, Inc.
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* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#include <autoconf.h>
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#if defined(CONFIG_SOC_XILINX_ZYNQMP_RPU)
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#include <arch/arm/aarch32/cortex_r/scripts/linker.ld>
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#endif
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