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devicetree: Remove DT_SRAM_{BASE_ADDRESS,SIZE}, use CONFIG_* versions

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The SRAM address and size are currently available as both
DT_SRAM_{BASE_ADDRESS,SIZE} and as CONFIG_SRAM_{BASE_ADDRESS,SIZE} (via
the Kconfig preprocessor).

Use the CONFIG_SRAM_* versions everywhere, and remove generation of the
DT_SRAM_* versions from gen_defines.py.

The Kconfig symbols currently depend on 'ARC || ARM || NIOS2 || X86'.
Not sure why, so I removed it.

It looks like no configuration files set CONFIG_SRAM_* at the moment, so
another option might be to use the DT_* symbols everywhere instead. Some
Kconfig.defconfig.series files add defaults to them though.

Also improve the help texts for CONFIG_SRAM_* to say that they normally
come from devicetree rather than configuration files.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit is contained in:
Ulf Magnusson 2019-12-26 16:08:19 +01:00 • committed by Johan Hedberg
commit def1f0e2d5
9 changed files with 22 additions and 23 deletions
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16
arch/Kconfig
View file

@ -85,8 +85,6 @@ config 64BIT
soc/**/Kconfig, or boards/**/Kconfig and the user should generally
avoid modifying it.
if ARC || ARM || NIOS2 || X86
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_SRAM := zephyr,sram
@ -94,17 +92,19 @@ config SRAM_SIZE
int "SRAM Size in kB"
default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM),0,K)
help
This option specifies the size of the SRAM in kB. It is normally set by
the board's defconfig file and the user should generally avoid modifying
it via the menu configuration.
The SRAM size in kB. The default value comes from /chosen/zephyr,sram in
devicetree. The user should generally avoid changing it via menuconfig or
in configuration files.
config SRAM_BASE_ADDRESS
hex "SRAM Base Address"
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))
help
This option specifies the base address of the SRAM on the board. It is
normally set by the board's defconfig file and the user should generally
avoid modifying it via the menu configuration.
The SRAM base address. The default value comes from from
/chosen/zephyr,sram in devicetree. The user should generally avoid
changing it via menuconfig or in configuration files.
if ARC || ARM || NIOS2 || X86
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_FLASH := zephyr,flash

6
boards/arm/udoo_neo_full_m4/doc/index.rst
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@ -209,9 +209,9 @@ DT_FLASH_SIZE macro to determine the region size and DT_FLASH_ADDR to determine
the address where the region begins.
If you want to have the data placed in the subregion of a memory, which will
likely be the case when using DDR, select "zephyr,sram=&sram" and set the
DT_SRAM_SIZE macro to determine the region size and DT_SRAM_ADDR to determine
the address where the region begins.
likely be the case when using DDR, select "zephyr,sram = &sram", which sets the
CONFIG_SRAM_SIZE macro to determine the region size and
CONFIG_SRAM_BASE_ADDRESS to determine the address where the region begins.
Otherwise set "zephyr,flash" and/or "zephyr,sram" to one of the predefined
regions:

2
include/arch/riscv/common/linker.ld
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@ -35,7 +35,7 @@ MEMORY
#ifdef CONFIG_XIP
ROM (rx) : ORIGIN = DT_FLASH_BASE_ADDRESS, LENGTH = KB(DT_FLASH_SIZE)
#endif
RAM (rwx) : ORIGIN = DT_SRAM_BASE_ADDRESS, LENGTH = KB(DT_SRAM_SIZE)
RAM (rwx) : ORIGIN = CONFIG_SRAM_BASE_ADDRESS, LENGTH = KB(CONFIG_SRAM_SIZE)
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
}

1
scripts/dts/gen_defines.py
View file

@ -68,7 +68,6 @@ def main():
out("COMPAT_{}".format(str2ident(compat)), 1)
# Derived from /chosen
write_addr_size(edt, "zephyr,sram", "SRAM")
write_addr_size(edt, "zephyr,ccm", "CCM")
write_addr_size(edt, "zephyr,dtcm", "DTCM")
write_addr_size(edt, "zephyr,ipc_shm", "IPC_SHM")

4
soc/riscv/openisa_rv32m1/linker.ld
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@ -56,8 +56,8 @@
#endif
#define RAM_BASE DT_SRAM_BASE_ADDRESS
#define RAM_SIZE KB(DT_SRAM_SIZE)
#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define RAM_SIZE KB(CONFIG_SRAM_SIZE)
MEMORY
{

4
soc/riscv/openisa_rv32m1/soc.h
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@ -105,7 +105,7 @@ void soc_interrupt_init(void);
#endif
/* Newlib hooks (and potentially other things) use these defines. */
#define RISCV_RAM_SIZE KB(DT_SRAM_SIZE)
#define RISCV_RAM_BASE DT_SRAM_BASE_ADDRESS
#define RISCV_RAM_SIZE KB(CONFIG_SRAM_SIZE)
#define RISCV_RAM_BASE CONFIG_SRAM_BASE_ADDRESS
#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_H_ */

4
soc/riscv/riscv-privilege/miv/soc.h
View file

@ -55,7 +55,7 @@
#define RISCV_MTIMECMP_BASE 0x44004000
/* lib-c hooks required RAM defined variables */
#define RISCV_RAM_BASE DT_SRAM_BASE_ADDRESS
#define RISCV_RAM_SIZE KB(DT_SRAM_SIZE)
#define RISCV_RAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define RISCV_RAM_SIZE KB(CONFIG_SRAM_SIZE)
#endif /* __RISCV32_MIV_SOC_H_ */

4
soc/riscv/riscv-privilege/sifive-freedom/soc.h
View file

@ -41,7 +41,7 @@
#define SIFIVE_BACKUP_REG_BASE 0x10000080
/* lib-c hooks required RAM defined variables */
#define RISCV_RAM_BASE DT_SRAM_BASE_ADDRESS
#define RISCV_RAM_SIZE KB(DT_SRAM_SIZE)
#define RISCV_RAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define RISCV_RAM_SIZE KB(CONFIG_SRAM_SIZE)
#endif /* __RISCV_SIFIVE_FREEDOM_SOC_H_ */

4
soc/xtensa/intel_s1000/dts_fixup.h
View file

@ -12,8 +12,8 @@
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_80800_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_80800_CLOCK_FREQUENCY
#define DT_L2_SRAM_BASE DT_SRAM_BASE_ADDRESS
#define DT_L2_SRAM_SIZE DT_SRAM_SIZE * 1024
#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024
#define DT_LP_SRAM_BASE DT_INST_1_MMIO_SRAM_BASE_ADDRESS
#define DT_LP_SRAM_SIZE DT_INST_1_MMIO_SRAM_SIZE