Handle PECI command PING properly, also get Write FCS Byte as a check.
Now it is possible to perform a PECI Ping without crashing the bus or
blocking it for subsequent PECI transactions.
It is also possible to check whether the Ping was sucessful
or not with the Write FCS Byte.
Signed-off-by: Johannes Meister <johannes.meister@kontron.com>
STM32H7 series offer alias addresses to access some registers that could
be accessed by the M4 core on dual core variants.
For instance RCC_AHB3ENR could be accessed at following offsets:
- 0x0D4: Accessible from both cores
- 0x134: Accessible from C1 (M7) core
- 0x194: Accessible from C2 (M4) core (if any)
For most single core H7 variants, the two first addresses were accessible,
but for some others (stm32h7ax/stm32h7bx), only the 'C1 accessible'
was available.
This fact used to be hidden by the use of LL API to access these registers,
providing the required abstraction (an mainly using the first alias
when possible to simplify implementation).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of computing hclk freq use for flash latency setting after
setting the PLLs, do it right at the beginning of the function.
Indeed, first step of PLL configuration is to switch back sysclock
to HSI source (in case it was initially PLL).
In that case, flash latency is theoretically set in consistency with PLL
driver hclk. So we should "measure" hclk freq at that step rather than
once sysclock is back on HSI.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is the actual hclk freq (ie core clock);
Remove use of intermediate new_hclk_freq to fix and simplify code.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Some specific F1 variants don't handle flash latency.
Put flash latency dealing code under dedicated switch.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Review code style in set_up_fixed_clock_sources() for better
readability.
Use of 'if (IS_ENABLED(STM32_MSI_ENABLED))' inside '#if STM32_MSI_ENABLED'
is redundant but intentional as it is in line with remaining part of the
function (HSE/HSI cases).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
On some parts, it could be required to use steps before applying
highest frequencies.
This was previously done as part of LL_PLL_ConfigSystemClock_FOO
utility functions which are no more used.
Use device tree to mention when this is required and implement it
in stm32_clock_control_init().
Additionally, fix the calls tp LL_RCC_SetAHBPrescaler, which require
use of ahb_prescaler helper.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Introduce a set_up_pll configuration function and make PLL configuration
an elementary step of the whole system clock configuration.
To implement this new, function make use of the existing series specific
files which allows series specific configuration when required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Group fixed clocks inits in a unique set_up function.
Each clock is initialized depending on its dts status.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Simplify and clean up driver code using STM32 clocks DT based macros.
Added STM32_FLASH_PRESCALER macro for this purpose.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Factorize setting of frequency for busses.
Additionally, factorize SysCoreClock update.
The operations are now done twice in case of PLL since they are part
of LL utils PLL configuration function, but they are removed in next
commits.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Take advantage of previous work to configure PLL and remove
usage of LL_PLL1_ConfigSystemClock_FOO utils functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that fixed clocks are enabled in a single function, a
bunch of functions could now be removed.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move fixed clocks initialization to a single function.
Benefit is they could now be enabled independently of the
main clock configuration based on dts status and then be
used by peripherals even is not part of the main clock tree.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Flash latency setting could be factorized in a single location,
rather than split in each clock setting function.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move prescaler settings to the clock_control_init function.
At this step they will be set up twice in PLL case, this will
be fixed in a next step.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Set bus binding values using registers offset values.
As a consequence update driver to take this into account
in clock_on and clock_off functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a check to avoid invalidating the cache when the latter is disabled.
Indeed, doing so can lead to a bus fault.
Signed-off-by: Thomas Altenbach <taltenbach@witekio.com>
Update the semihost_console implementation to use the semihost API
instead of manually constructing the supervisor calls.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Control the usage of semihosting with a dedicated symbol, instead of
implying semihosting from the usage of `SEMIHOST_CONSOLE`. This allows
semihosting to be used without the semihost console.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Do not soft-reset device when changing timing parameters as the
soft-reset will discard the configured CAN controller mode.
Fixes: #44837
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename CONFIG_CAN_STM32_CLOCK_DIVISOR to
CONFIG_CAN_STM32FD_CLOCK_DIVISOR to match driver Kconfig name.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add support for selecting the CAN clock source. Change previously
hardcoded value of PCLK1 to HSE.
Fixes: #44985
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Clean up of pin signals definitions previously used
by the pinmux driver, now deprecated by the use of
the pinctrl API.
Refactor device tree macros usage to make usage of
SPI instances more general.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Differently from ESP32, the ESP32-S2 SoC has native
hal support to reset its own I2C FSM in case of failure.
This commit removes warnings related to unused reset
logic, which does not really apply to ESP32-S2.
It also removes code and data structures related to pin
information from the build when the target SoC supports
hardware mechanisms to reset the I2C FSM.
Finally, it checks at compile time if the preconditions
for correct bus recovery are being met.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Clean up of pin signals definitions previously used
by the pinmux driver, now deprecated by the use of
the pinctrl API.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
though using pinctrl's subsystem, the I2C driver
keeps pin information in case of communication
failure. This information is needed in case of
FSM failure.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Add a separate macro for registering offloaded sockets implementation,
along with information in the structure whether the implementation is
offloaded or not. This allows to differentiate between native and
offloaded socket implementations, which is critical for binding socket
API with an interface.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
Instead of keeping a boolean informing whether a network interface is
offloaded at socket layer or not, keep a pointer to a function which
allows to create an offloaded socket. Native interfaces keep this as
NULL, while for offloaded interfaces it allows to connect an offloaded
socket implementation with an interface.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
update pin control implementation to use offsets for pin registers
instead of pin/port combination, to permit additional flexibility for
lpc devices with non contiguous register layouts. Update LPC55s69 pin
control names to align with newly generated pin control header.
This change also requires an update to the NXP HAL to use the new pin
control headers with offsets.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Do not silently ignore attempts to set an unsupported mode. Return
-ENOTSUP instead.
Fixes: #44706
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
