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drivers/clock_control: stm32_common: Add elementary PLL configuration step

Browse source 
Introduce a set_up_pll configuration function and make PLL configuration
an elementary step of the whole system clock configuration.

To implement this new, function make use of the existing series specific
files which allows series specific configuration when required.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-03-23 15:34:16 +01:00 • committed by Carles Cufí
commit c4ff7d1e19
9 changed files with 255 additions and 207 deletions
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196
drivers/clock_control/clock_stm32_ll_common.c
View file

@ -61,32 +61,6 @@
#define STM32WL_DUAL_CORE
#endif
/**
* @brief fill in AHB/APB buses configuration structure
*/
static void config_bus_clk_init(LL_UTILS_ClkInitTypeDef *clk_init)
{
#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(STM32WL_DUAL_CORE)
clk_init->CPU2CLKDivider = ahb_prescaler(STM32_CPU2_PRESCALER);
#endif
#if defined(CONFIG_SOC_SERIES_STM32WBX)
clk_init->CPU1CLKDivider = ahb_prescaler(STM32_CPU1_PRESCALER);
clk_init->AHB4CLKDivider = ahb_prescaler(STM32_AHB4_PRESCALER);
#elif defined(CONFIG_SOC_SERIES_STM32WLX)
clk_init->CPU1CLKDivider = ahb_prescaler(STM32_CPU1_PRESCALER);
clk_init->AHB3CLKDivider = ahb_prescaler(STM32_AHB3_PRESCALER);
#else
clk_init->AHBCLKDivider = ahb_prescaler(STM32_AHB_PRESCALER);
#endif /* CONFIG_SOC_SERIES_STM32WBX */
clk_init->APB1CLKDivider = apb1_prescaler(STM32_APB1_PRESCALER);
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \
!defined (CONFIG_SOC_SERIES_STM32G0X)
clk_init->APB2CLKDivider = apb2_prescaler(STM32_APB2_PRESCALER);
#endif
}
static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
{
return clock / prescaler;
@ -354,6 +328,60 @@ static inline void stm32_clock_control_mco_init(void)
#endif /* CONFIG_CLOCK_STM32_MCO2_SRC_NOCLOCK */
}
__unused
static int set_up_plls(void)
{
#if defined(STM32_PLL_ENABLED)
int r;
/*
* Case of chain-loaded applications:
* Switch to HSI and disable the PLL before configuration.
* (Switching to HSI makes sure we have a SYSCLK source in
* case we're currently running from the PLL we're about to
* turn off and reconfigure.)
*
*/
if (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {
stm32_clock_switch_to_hsi(LL_RCC_SYSCLK_DIV_1);
}
LL_RCC_PLL_Disable();
#ifdef CONFIG_SOC_SERIES_STM32F7X
/* Assuming we stay on Power Scale default value: Power Scale 1 */
if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC > 180000000) {
LL_PWR_EnableOverDriveMode();
while (LL_PWR_IsActiveFlag_OD() != 1) {
/* Wait for OverDrive mode ready */
}
LL_PWR_EnableOverDriveSwitching();
while (LL_PWR_IsActiveFlag_ODSW() != 1) {
/* Wait for OverDrive switch ready */
}
}
#endif
#if STM32_PLL_Q_DIVISOR
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ,
STM32_PLL_Q_DIVISOR
<< RCC_PLLCFGR_PLLQ_Pos);
#endif
r = config_pll_sysclock();
if (r < 0) {
return -ENOTSUP;
}
/* Enable PLL */
LL_RCC_PLL_Enable();
while (LL_RCC_PLL_IsReady() != 1U) {
/* Wait for PLL ready */
}
#endif /* STM32_PLL_ENABLED */
return 0;
}
static void set_up_fixed_clock_sources(void)
{
@ -433,15 +461,13 @@ static void set_up_fixed_clock_sources(void)
*/
int stm32_clock_control_init(const struct device *dev)
{
LL_UTILS_ClkInitTypeDef s_ClkInitStruct;
uint32_t new_hclk_freq;
uint32_t old_flash_freq;
uint32_t new_flash_freq;
int r;
ARG_UNUSED(dev);
/* configure clock for AHB/APB buses */
config_bus_clk_init((LL_UTILS_ClkInitTypeDef *)&s_ClkInitStruct);
/* Some clocks would be activated by default */
config_enable_default_clocks();
@ -460,126 +486,34 @@ int stm32_clock_control_init(const struct device *dev)
LL_SetFlashLatency(new_flash_freq);
}
/* Set up indiviual enabled clocks */
set_up_fixed_clock_sources();
/* Set up PLLs */
r = set_up_plls();
if (r < 0) {
return r;
}
#if STM32_SYSCLK_SRC_PLL
LL_UTILS_PLLInitTypeDef s_PLLInitStruct;
/* configure PLL input settings */
config_pll_init(&s_PLLInitStruct);
if (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {
/*
* Case of chain-loaded applications
* Switch to HSI and disable the PLL before configuration.
* (Switching to HSI makes sure we have a SYSCLK source in
* case we're currently running from the PLL we're about to
* turn off and reconfigure.)
*
* Don't use s_ClkInitStruct.AHBCLKDivider as the AHB
* prescaler here. In this configuration, that's the value to
* use when the SYSCLK source is the PLL, not HSI.
*/
stm32_clock_switch_to_hsi(LL_RCC_SYSCLK_DIV_1);
LL_RCC_PLL_Disable();
/* Set PLL as System Clock Source */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {
}
#ifdef CONFIG_SOC_SERIES_STM32F7X
/* Assuming we stay on Power Scale default value: Power Scale 1 */
if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC > 180000000) {
LL_PWR_EnableOverDriveMode();
while (LL_PWR_IsActiveFlag_OD() != 1) {
/* Wait for OverDrive mode ready */
}
LL_PWR_EnableOverDriveSwitching();
while (LL_PWR_IsActiveFlag_ODSW() != 1) {
/* Wait for OverDrive switch ready */
}
}
#endif
#if STM32_PLL_Q_DIVISOR
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ,
STM32_PLL_Q_DIVISOR
<< RCC_PLLCFGR_PLLQ_Pos);
#endif /* STM32_PLL_Q_DIVISOR */
#if STM32_PLL_SRC_MSI
/* Set MSI Range */
#if defined(RCC_CR_MSIRGSEL)
LL_RCC_MSI_EnableRangeSelection();
#endif /* RCC_CR_MSIRGSEL */
LL_RCC_MSI_SetRange(STM32_MSI_RANGE << RCC_CR_MSIRANGE_Pos);
LL_RCC_MSI_SetCalibTrimming(0);
#if STM32_MSI_PLL_MODE
#ifndef STM32_LSE_ENABLED
#error "MSI Hardware auto calibration requires LSE clock activation"
#endif
/* Enable MSI hardware auto calibration */
LL_RCC_MSI_EnablePLLMode();
#endif
/* Switch to PLL with MSI as clock source */
LL_PLL_ConfigSystemClock_MSI(&s_PLLInitStruct, &s_ClkInitStruct);
#elif STM32_PLL_SRC_HSI
/* Switch to PLL with HSI as clock source */
LL_PLL_ConfigSystemClock_HSI(&s_PLLInitStruct, &s_ClkInitStruct);
#elif STM32_PLL_SRC_HSE
#ifndef CONFIG_SOC_SERIES_STM32WLX
int hse_bypass;
if (IS_ENABLED(STM32_HSE_BYPASS)) {
hse_bypass = LL_UTILS_HSEBYPASS_ON;
} else {
hse_bypass = LL_UTILS_HSEBYPASS_OFF;
}
#else
if (IS_ENABLED(STM32_HSE_TCXO)) {
LL_RCC_HSE_EnableTcxo();
}
if (IS_ENABLED(STM32_HSE_DIV2)) {
LL_RCC_HSE_EnableDiv2();
}
#endif
/* Switch to PLL with HSE as clock source */
LL_PLL_ConfigSystemClock_HSE(
#if !defined(CONFIG_SOC_SERIES_STM32WBX) && !defined(CONFIG_SOC_SERIES_STM32WLX)
CONFIG_CLOCK_STM32_HSE_CLOCK,
#endif
#ifndef CONFIG_SOC_SERIES_STM32WLX
hse_bypass,
#endif
&s_PLLInitStruct,
&s_ClkInitStruct);
#endif /* STM32_PLL_SRC_* */
#elif STM32_SYSCLK_SRC_HSE
/* Set HSE as SYSCLCK source */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
LL_RCC_SetAHBPrescaler(STM32_CORE_PRESCALER);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
}
#elif STM32_SYSCLK_SRC_MSI
/* Set MSI as SYSCLCK source */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSI);
LL_RCC_SetAHBPrescaler(STM32_CORE_PRESCALER);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI) {
}
#elif STM32_SYSCLK_SRC_HSI
stm32_clock_switch_to_hsi(STM32_CORE_PRESCALER);
#endif /* STM32_SYSCLK_SRC_... */
/* If freq not increased, set flash latency after all clock setting */

6
drivers/clock_control/clock_stm32_ll_common.h
View file

@ -32,9 +32,9 @@
#define MCO2_SOURCE LL_RCC_MCO2SOURCE_PLLCLK
#endif
#if STM32_SYSCLK_SRC_PLL
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit);
#endif /* STM32_SYSCLK_SRC_PLL */
#ifdef STM32_SYSCLK_SRC_PLL
int config_pll_sysclock(void);
#endif
void config_enable_default_clocks(void);
/* function exported to the soc power.c */

36
drivers/clock_control/clock_stm32f0_f3.c
View file

@ -19,10 +19,12 @@
#if STM32_SYSCLK_SRC_PLL
/**
* @brief fill in pll configuration structure
* @brief Set up pll configuration
*/
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
int config_pll_sysclock(void)
{
uint32_t pll_source, pll_mul, pll_div;
/*
* PLL MUL
* 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
@ -31,8 +33,7 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
* ...
* 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
*/
pllinit->PLLMul = ((STM32_PLL_MULTIPLIER - 2)
<< RCC_CFGR_PLLMUL_Pos);
pll_mul = ((STM32_PLL_MULTIPLIER - 2) << RCC_CFGR_PLLMUL_Pos);
/*
* PLL PREDIV
@ -42,6 +43,8 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
* ...
* 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
*/
pll_div = STM32_PLL_PREDIV - 1;
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
/*
* PREDIV1 support is a specific RCC configuration present on
@ -49,10 +52,31 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
* STM32F030xC, STM32F302xE, STM32F303xE and STM32F39xx
* cf Reference manual for more details
*/
pllinit->PLLDiv = STM32_PLL_PREDIV - 1;
/* Configure PLL source */
if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
pll_source = LL_RCC_PLLSOURCE_HSE;
} else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
pll_source = LL_RCC_PLLSOURCE_HSI;
} else {
return -ENOTSUP;
}
LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul, pll_div);
#else
pllinit->Prediv = STM32_PLL_PREDIV - 1;
/* Configure PLL source */
if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
pll_source = LL_RCC_PLLSOURCE_HSE | pll_div;
} else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
pll_source = LL_RCC_PLLSOURCE_HSI_DIV_2;
} else {
return -ENOTSUP;
}
LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul);
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
return 0;
}
#endif /* STM32_SYSCLK_SRC_PLL */

92
drivers/clock_control/clock_stm32f1.c
View file

@ -17,24 +17,19 @@
#if STM32_SYSCLK_SRC_PLL
/*
* Select PLL source for STM32F1 Connectivity line devices (STM32F105xx and
* STM32F107xx).
* Both flags are defined in STM32Cube LL API. Keep only the selected one.
*/
#if STM32_PLL_SRC_PLL2
#undef RCC_PREDIV1_SOURCE_HSE
#else
#undef RCC_PREDIV1_SOURCE_PLL2
#endif /* STM32_PLL_SRC_PLL2 */
/**
* @brief fill in pll configuration structure
* @brief Set up pll configuration
*/
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
int config_pll_sysclock(void)
{
uint32_t pll_source, pll_mul, pll_div;
/*
* PLLMUL on SOC_STM32F10X_DENSITY_DEVICE
* 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
@ -49,46 +44,57 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
* 9 -> LL_RCC_PLL_MUL_9 -> 0x001C0000
* 13 -> LL_RCC_PLL_MUL_6_5 -> 0x00340000
*/
pllinit->PLLMul = ((STM32_PLL_MULTIPLIER - 2)
<< RCC_CFGR_PLLMULL_Pos);
pll_mul = ((STM32_PLL_MULTIPLIER - 2) << RCC_CFGR_PLLMULL_Pos);
#if STM32_PLL_SRC_HSI
/* In case PLL source is HSI, prediv is 2 */
pllinit->Prediv = LL_RCC_PREDIV_DIV_2;
#else
/* In case PLL source is not HSI, set prediv case by case */
if (!IS_ENABLED(STM32_PLL_SRC_HSI)) {
/* In case PLL source is not HSI, set prediv case by case */
#ifdef CONFIG_SOC_STM32F10X_DENSITY_DEVICE
/* PLL prediv */
#if STM32_PLL_XTPRE
/*
* SOC_STM32F10X_DENSITY_DEVICE:
* PLLXPTRE (depends on PLL source HSE)
* HSE/2 used as PLL source
*/
pllinit->Prediv = LL_RCC_PREDIV_DIV_2;
/* PLL prediv */
if (IS_ENABLED(STM32_PLL_XTPRE)) {
/*
* SOC_STM32F10X_DENSITY_DEVICE:
* PLLXPTRE (depends on PLL source HSE)
* HSE/2 used as PLL source
*/
pll_div = LL_RCC_PREDIV_DIV_2;
} else {
/*
* SOC_STM32F10X_DENSITY_DEVICE:
* PLLXPTRE (depends on PLL source HSE)
* HSE used as direct PLL source
*/
pll_div = LL_RCC_PREDIV_DIV_1;
}
#else
/*
* SOC_STM32F10X_DENSITY_DEVICE:
* PLLXPTRE (depends on PLL source HSE)
* HSE used as direct PLL source
*/
pllinit->Prediv = LL_RCC_PREDIV_DIV_1;
#endif /* STM32_PLL_XTPRE */
#else
/*
* SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
* 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
* 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
* 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
* ...
* 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
*/
pllinit->Prediv = STM32_PLL_PREDIV - 1;
/*
* SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
* 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
* 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
* 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
* ...
* 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
*/
pll_div = STM32_PLL_PREDIV - 1;
#endif /* CONFIG_SOC_STM32F10X_DENSITY_DEVICE */
}
#endif /* STM32_PLL_SRC_HSI */
/* Configure PLL source */
if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
pll_source = LL_RCC_PLLSOURCE_HSI_DIV_2;
} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
pll_source = LL_RCC_PLLSOURCE_HSE | pll_div;
#if defined(RCC_CFGR2_PREDIV1SRC)
} else if (IS_ENABLED(STM32_PLL_SRC_PLL2)) {
pll_source = LL_RCC_PLLSOURCE_PLL2 | pll_div;
#endif
} else {
return -ENOTSUP;
}
LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul);
return 0;
}
#endif /* STM32_SYSCLK_SRC_PLL */
/**

25
drivers/clock_control/clock_stm32f2_f4_f7.c
View file

@ -26,13 +26,28 @@
#define pllp(v) z_pllp(v)
/**
* @brief fill in pll configuration structure
* @brief Set up pll configuration
*/
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
int config_pll_sysclock(void)
{
pllinit->PLLM = pllm(STM32_PLL_M_DIVISOR);
pllinit->PLLN = STM32_PLL_N_MULTIPLIER;
pllinit->PLLP = pllp(STM32_PLL_P_DIVISOR);
uint32_t pll_source, pll_m, pll_n, pll_p;
pll_n = STM32_PLL_N_MULTIPLIER;
pll_m = pllm(STM32_PLL_M_DIVISOR);
pll_p = pllp(STM32_PLL_P_DIVISOR);
/* Configure PLL source */
if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
pll_source = LL_RCC_PLLSOURCE_HSI;
} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
pll_source = LL_RCC_PLLSOURCE_HSE;
} else {
return -ENOTSUP;
}
LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_m, pll_n, pll_p);
return 0;
}
#endif /* STM32_SYSCLK_SRC_PLL */

27
drivers/clock_control/clock_stm32g0.c
View file

@ -27,13 +27,30 @@
#define pllr(v) z_pllr(v)
/**
* @brief Fill PLL configuration structure
* @brief Set up pll configuration
*/
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
int config_pll_sysclock(void)
{
pllinit->PLLN = STM32_PLL_N_MULTIPLIER;
pllinit->PLLM = pll_div(STM32_PLL_M_DIVISOR);
pllinit->PLLR = pllr(STM32_PLL_R_DIVISOR);
uint32_t pll_source, pll_m, pll_n, pll_r;
pll_n = STM32_PLL_N_MULTIPLIER;
pll_m = pll_div(STM32_PLL_M_DIVISOR);
pll_r = pllr(STM32_PLL_R_DIVISOR);
/* Configure PLL source */
if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
pll_source = LL_RCC_PLLSOURCE_HSI;
} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
pll_source = LL_RCC_PLLSOURCE_HSE;
} else {
return -ENOTSUP;
}
LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_m, pll_n, pll_r);
LL_RCC_PLL_EnableDomain_SYS();
return 0;
}
#endif /* STM32_SYSCLK_SRC_PLL */

27
drivers/clock_control/clock_stm32g4.c
View file

@ -26,18 +26,35 @@
#define pllr(v) z_pllr(v)
/**
* @brief fill in pll configuration structure
* @brief Set up pll configuration
*/
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
int config_pll_sysclock(void)
{
pllinit->PLLM = pllm(STM32_PLL_M_DIVISOR);
pllinit->PLLN = STM32_PLL_N_MULTIPLIER;
pllinit->PLLR = pllr(STM32_PLL_R_DIVISOR);
uint32_t pll_source, pll_m, pll_n, pll_r;
/* set power boost mode for sys clock greater than 150MHz */
if (sys_clock_hw_cycles_per_sec() >= MHZ(150)) {
LL_PWR_EnableRange1BoostMode();
}
pll_n = STM32_PLL_N_MULTIPLIER;
pll_m = pllm(STM32_PLL_M_DIVISOR);
pll_r = pllr(STM32_PLL_R_DIVISOR);
/* Configure PLL source */
if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
pll_source = LL_RCC_PLLSOURCE_HSI;
} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
pll_source = LL_RCC_PLLSOURCE_HSE;
} else {
return -ENOTSUP;
}
LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_m, pll_n, pll_r);
LL_RCC_PLL_EnableDomain_SYS();
return 0;
}
#endif /* STM32_SYSCLK_SRC_PLL */

23
drivers/clock_control/clock_stm32l0_l1.c
View file

@ -26,12 +26,27 @@
#define pll_div(v) z_pll_div(v)
/**
* @brief Fill PLL configuration structure
* @brief Set up pll configuration
*/
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
int config_pll_sysclock(void)
{
pllinit->PLLMul = pll_mul(STM32_PLL_MULTIPLIER);
pllinit->PLLDiv = pll_div(STM32_PLL_DIVISOR);
uint32_t pll_source, pll_mul, pll_div;
pll_mul = pll_mul(STM32_PLL_MULTIPLIER);
pll_div = pll_div(STM32_PLL_DIVISOR);
/* Configure PLL source */
if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
pll_source = LL_RCC_PLLSOURCE_HSI;
} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
pll_source = LL_RCC_PLLSOURCE_HSE;
} else {
return -ENOTSUP;
}
LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul, pll_div);
return 0;
}
#endif /* STM32_SYSCLK_SRC_PLL */

30
drivers/clock_control/clock_stm32l4_l5_wb_wl.c
View file

@ -27,19 +27,39 @@
#define pllr(v) z_pllr(v)
/**
* @brief fill in pll configuration structure
* @brief Set up pll configuration
*/
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
int config_pll_sysclock(void)
{
pllinit->PLLM = pllm(STM32_PLL_M_DIVISOR);
pllinit->PLLN = STM32_PLL_N_MULTIPLIER;
pllinit->PLLR = pllr(STM32_PLL_R_DIVISOR);
uint32_t pll_source, pll_m, pll_n, pll_r;
#ifdef PWR_CR5_R1MODE
/* set power boost mode for sys clock greater than 80MHz */
if (sys_clock_hw_cycles_per_sec() >= MHZ(80)) {
LL_PWR_EnableRange1BoostMode();
}
#endif /* PWR_CR5_R1MODE */
pll_n = STM32_PLL_N_MULTIPLIER;
pll_m = pllm(STM32_PLL_M_DIVISOR);
pll_r = pllr(STM32_PLL_R_DIVISOR);
/* Configure PLL source */
if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
pll_source = LL_RCC_PLLSOURCE_HSI;
} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
pll_source = LL_RCC_PLLSOURCE_HSE;
} else if (IS_ENABLED(STM32_PLL_SRC_MSI)) {
pll_source = LL_RCC_PLLSOURCE_MSI;
} else {
return -ENOTSUP;
}
LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_m, pll_n, pll_r);
LL_RCC_PLL_EnableDomain_SYS();
return 0;
}
#endif /* STM32_SYSCLK_SRC_PLL */