include/dt-bindings: clocks: stm32h7: Use _C1_ registers offset
STM32H7 series offer alias addresses to access some registers that could be accessed by the M4 core on dual core variants. For instance RCC_AHB3ENR could be accessed at following offsets: - 0x0D4: Accessible from both cores - 0x134: Accessible from C1 (M7) core - 0x194: Accessible from C2 (M4) core (if any) For most single core H7 variants, the two first addresses were accessible, but for some others (stm32h7ax/stm32h7bx), only the 'C1 accessible' was available. This fact used to be hidden by the use of LL API to access these registers, providing the required abstraction (an mainly using the first alias when possible to simplify implementation). Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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2 changed files with 19 additions and 11 deletions
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@ -153,6 +153,14 @@
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#endif
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#endif /* CONFIG_CPU_CORTEX_M7 */
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#if defined(CONFIG_CPU_CORTEX_M7)
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/* Offset to access bus clock registers from M7 (or only) core */
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#define STM32H7_BUS_CLK_REG DT_REG_ADDR(DT_NODELABEL(rcc))
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#elif defined(CONFIG_CPU_CORTEX_M4)
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/* Offset to access bus clock registers from M4 core */
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#define STM32H7_BUS_CLK_REG DT_REG_ADDR(DT_NODELABEL(rcc)) + 0x60
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#endif
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static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
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{
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return clock / prescaler;
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@ -329,7 +337,7 @@ static inline int stm32_clock_control_on(const struct device *dev,
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z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
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reg = (uint32_t *)(STM32H7_BUS_CLK_REG + pclken->bus);
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reg_val = *reg;
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reg_val |= pclken->enr;
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*reg = reg_val;
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@ -355,7 +363,7 @@ static inline int stm32_clock_control_off(const struct device *dev,
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z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
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reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
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reg = (uint32_t *)(STM32H7_BUS_CLK_REG + pclken->bus);
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reg_val = *reg;
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reg_val &= ~pclken->enr;
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*reg = reg_val;
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