Only add the filter ID offset for extended CAN-ID filters if the filter
was added successfully. Raise log level from info to warning if filter
addition failed but only log it once.
Fix bounds check for removing an extended CAN-ID filter.
Fixes: #44721
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Commit a50b69dfb7 introduced a work-around
for FlexCAN errata 5461 and 5829, but neglegted to take the RX mailbox
offset into account when calculating maximum number of mailboxes
allocated for RX/TX.
Fixes: #44724
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Remove support for the optional API function can_get_max_filters() from
the STM32 bxCAN driver for now.
The function returns the Kconfig value for the maximum number of filters
but the true number of supported filters may be different due to the
filter nature of the STM32 bxCAN driver implementation.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Adds hda link in and out drivers. The link in and link
out channels of HDA have small differences
with the host channels. Updates the existing
cavs_hda drivers and code to account for these
differences.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
all the consumers of the obsolete pinmux driver is
updated to use pinctrl API, this commit removes
the pinmux driver and assosciated sections.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
This commit has the necessary changes to update the consumers
of pinmux driver(SPI, I2C, UART) and update the board specific
files to use the pinctrl interface.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Add pinctrl driver for CC13XX/CC26XX family of SoCs
to facilitate transition from pinmux to pinctrl.
`IOCPortConfigureSet()` from TI hal driverlib used to
implement the generic pinctrl driver.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
1.Declare the member type to match the kscan_it8xxx2_regs, so
we needn't to transform the local structure in the function.
2.Stop using DRV_CONFIG, DRV_DATA, DRV_REG macros.
3.Delete unused register defines.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This PR enables the Ansynchronous UART API for using the MCUX drivers.
It is tested on the RT1062EVKB.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
This PR fixes up the Scatter-Gather EDMA mode for the MCUX EDMA Driver,
as well as enabling the dma reload feature for the same EDMA Driver.
Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
Multiple instances of the device would have inadvertently shared the
LLI pool potentially causing nasty bugs.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Only initialize the FlexCAN IP core once since initialzing it has the
side effect of resetting the IP core and thus clearing previous settings
such as RX filters.
Fixes: #44680
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
redefine all the stm32 flash register bit Name from
FLASH_NSCR_xxx to FLASH_STM32_FLASH_NSCR_xxx
in all the zephyr drivers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Adds the stm32u5 flash controller driver for this serie
to the existing stm32l5 flash driver part
Only 1 or 2 MB devices exist today (4MB is possible in the future).
This flash controller driver is adapted from the flash_stm32l5.c
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This adds the stm32U5 soc family to the flash driver
The flash controller has particular register names in the Non-Secure
area to be adapted for the driver.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The SAM0 fast-path implementation was broken, and partially fixed in
commits 8181eed and 8a99bd0...
This patch resolves an issue where the MSB is always zero on SAML21
parts, and appears to follow suit with the previous patches.
This patch also refreshes the commentary, and removes mention of the
"interleaved" operation that is no longer used - which appears to have
been problematic in the past.
In addition to this, it also resolves an off-by-one error in both the
fast_rx and fast_rxrx paths, which would have been tripped when
transmitting a zero-byte buffer.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
CAN in Automation (CiA) 301 v4.2.0 recommends a sample point location of
87.5% percent for all bitrates. However, some CAN controllers have
difficulties meeting this for higher bitrates.
Change can_set_bitrate() to use a sample point of 75.0% for bitrates
over 800 kbit/s, 80.0% for bitrates over 500 kbit/s, and 87.5% for all
other bitrates. This is in line with the sample point locations used by
the Linux kernel.
Regard a sample point error of more than +/- 5.0% as an error in setting
the bitrate. Previously, any sample rate error was accepted without
providing any feedback to the caller. This is in line with the CAN
sample point calculation criteria used by the Linux kernel.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Value changed from 100us to 150us. Value was not enough upon softreset.
This value was arbitrarily chosen and should be changed if more
information on the subject is provided.
Fixes#43794
Signed-off-by: Diogo Correia <dcorreia@protonmail.com>
Read KBC Status register before reading KBC Data register
in kbc0_ibf_isr; since read data will clear status.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Modify the Microchip MEC172x I2C driver to use the device tree I2C
clock-frequency property and driver initialization time. Also, fixed
missing idle scaling register programming.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The cmd_write contains write verification that compares what has
been written with what it can read; the flash read operation
status was not checked which means that the bus or communication
problem was reported the same way as malformed write.
There have also been some optimization done by removal
of multiplications.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
The commit changes default buffer size for flash write operations
to be CONFIG_SHELL_ARGC_MAX dependent; there is no point to define
buffer longer than number of write bytes that will be extracted
from command line arguments.
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
We put disabling SOC interrupt enable register (IER) sequence in
between disable and enable core's global interrupt to prevent race
condition.
After core interrupt enable instruction has been executed, the new
configuration of IER has not yet been fully processed due to
asynchronization between core and SOC's source clock.
If SOC interrupt is fired under the above condition, we will get
IRQ number 0 in ISR due to IER disabling taken effect.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This way, when RTC is used as the generator, one PPI channel per each
configured PWM channel can be saved.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
