Handle PECI command PING properly, also get Write FCS Byte as a check.
Now it is possible to perform a PECI Ping without crashing the bus or
blocking it for subsequent PECI transactions.
It is also possible to check whether the Ping was sucessful
or not with the Write FCS Byte.
Signed-off-by: Johannes Meister <johannes.meister@kontron.com>
This is a follow-up to commit f4a0ddd8af.
Since the yellow LED and the SCK line of spi2 use the same pin
(P0.13), they cannot be used together. Consequently, the pin
should not be assigned to the same PWM instance as other pins
that drive LEDs, as the limitation of usage would apply to the
whole PWM instance (it acquires all the pins assigned to it on
initialization of the PWM driver, regardless of whether the PWM
signal is eventually generated on particular outputs or not).
Use a separate PWM instance (disabled by default) for driving
the yellow LED. Don't use the "nordic,invert" property for that
PWM, as the yellow LED is active high.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit f4a0ddd8af.
According to the schematic, the LED connected to the P1.09 pin is
active high. Therefore, the PWM1 instance that is configured to drive
the LED should not use the "nordic,invert" property.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
STM32H7 series offer alias addresses to access some registers that could
be accessed by the M4 core on dual core variants.
For instance RCC_AHB3ENR could be accessed at following offsets:
- 0x0D4: Accessible from both cores
- 0x134: Accessible from C1 (M7) core
- 0x194: Accessible from C2 (M4) core (if any)
For most single core H7 variants, the two first addresses were accessible,
but for some others (stm32h7ax/stm32h7bx), only the 'C1 accessible'
was available.
This fact used to be hidden by the use of LL API to access these registers,
providing the required abstraction (an mainly using the first alias
when possible to simplify implementation).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rework test_*_freq to test HCLK freq instead of SYSCLK one, as it is not
correct to compare CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC with SYSCLK.
Additionally, add a test to verify use of AHB prescaler.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of computing hclk freq use for flash latency setting after
setting the PLLs, do it right at the beginning of the function.
Indeed, first step of PLL configuration is to switch back sysclock
to HSI source (in case it was initially PLL).
In that case, flash latency is theoretically set in consistency with PLL
driver hclk. So we should "measure" hclk freq at that step rather than
once sysclock is back on HSI.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of testing SysClockFreq setting, we should instead check HCLK
setting which is the real zephyr CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
counterpart (core clock freq) and takes AHB prescaler setting into
account.
Additionally, update one test configuration to explicitly verify AHB
prescaler is correctly taken into account by clock driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC is the actual hclk freq (ie core clock);
Remove use of intermediate new_hclk_freq to fix and simplify code.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rework bindings documentation to clearly illustrate the role of ahb
(and cpu1) prescaler which defines the actual core clock frequency,
and not only a bus frequency.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Use enum to describe the range of allowed MSI values.
This will help to detect configuration issues earlier.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove L0 and L1 targets from "sysclksrc_msi_48" test case as this
MSI range 11 is not an allowed value on these series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Some specific F1 variants don't handle flash latency.
Put flash latency dealing code under dedicated switch.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
According to board documentation: "By default System
clock is driven by the MSI clock at 48MHz."
This is in line with rcc node dts configuration:
&rcc {
[...]
clocks = <&clk_msi>;
[...]
};
Though pll node is currently enabled, which is not in line with
current dts clocks description scheme and results to compilation
issue in clock_control driver.
Remove pll node configuration to fix this.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add new scheme clock bindings for 'common' series:
- stm32f1_clock.h > compatible with f0/f1/f3 series
- stm32f4_clock.h > compatible with f2/f4/f7 series
- stm32l0_clock.h > compatible with l0 series
- stm32l1_clock.h > compatible with l1 series
- stm32l4_clock.h > compatible with g4/l4/l5/wb series
- stm32wl_clock.h > compatible with wl series
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Review code style in set_up_fixed_clock_sources() for better
readability.
Use of 'if (IS_ENABLED(STM32_MSI_ENABLED))' inside '#if STM32_MSI_ENABLED'
is redundant but intentional as it is in line with remaining part of the
function (HSE/HSI cases).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
On some parts, it could be required to use steps before applying
highest frequencies.
This was previously done as part of LL_PLL_ConfigSystemClock_FOO
utility functions which are no more used.
Use device tree to mention when this is required and implement it
in stm32_clock_control_init().
Additionally, fix the calls tp LL_RCC_SetAHBPrescaler, which require
use of ahb_prescaler helper.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Introduce a set_up_pll configuration function and make PLL configuration
an elementary step of the whole system clock configuration.
To implement this new, function make use of the existing series specific
files which allows series specific configuration when required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Group fixed clocks inits in a unique set_up function.
Each clock is initialized depending on its dts status.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Simplify and clean up driver code using STM32 clocks DT based macros.
Added STM32_FLASH_PRESCALER macro for this purpose.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Factorize setting of frequency for busses.
Additionally, factorize SysCoreClock update.
The operations are now done twice in case of PLL since they are part
of LL utils PLL configuration function, but they are removed in next
commits.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Take advantage of previous work to configure PLL and remove
usage of LL_PLL1_ConfigSystemClock_FOO utils functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that fixed clocks are enabled in a single function, a
bunch of functions could now be removed.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move fixed clocks initialization to a single function.
Benefit is they could now be enabled independently of the
main clock configuration based on dts status and then be
used by peripherals even is not part of the main clock tree.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Flash latency setting could be factorized in a single location,
rather than split in each clock setting function.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move prescaler settings to the clock_control_init function.
At this step they will be set up twice in PLL case, this will
be fixed in a next step.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Introduce a new scheme to define clock bingings on u5.
In a next steps, this new scheme will allow to provide u5 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
On some series (H7, U5), it is possible define clock configuration
with disabled PLL outputs.
In that case, it is legit that matching pll property is not available.
Define corresponding STM32_PLLX_Y_DIVISOR macros using DT_PROP_OR
to avoid build issues in case prop is not available.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Set bus binding values using registers offset values.
As a consequence update driver to take this into account
in clock_on and clock_off functions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This new binding allows to work on providing stm32h7 specific
alternate and complementary device clocks.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
If a Zephyr binary is booted on the Zynq-7000 not via JTAG download,
but via u-boot's ELF boot function instead, Zephyr will have to revert
certain changes made by u-boot in order to boot properly:
- clear the ICache/DCache enable, branch prediction enable and
strict alignment enforcement enable bits in the SCTLR register.
By default, u-boot will also set up the MMU prior to Zephyr
doing so as well, this can be avoided by changing the u-boot
build configuration. Therefore, the MMU enable bit is not changed
at this point.
- set the VBAR register to 0. U-boot moves the interrupt vector
table to a non-standard location using the VBAR register (no
change is made by u-boot for SCTLR.V, only VBAR is changed
to a non-zero memory location).
Without these changes, Zephyr will crash upon the first context
switch at latest, when SVC is invoked and u-boot's vector table
is used rather than the vectors copied to address zero by Zephyr.
In order to perform these changes before coming anwhere near the
MMU / device driver / kernel initialization stages or even the
first context switch, the z_arm_platform_init hook is used, which
is now enabled for the Zynq via the Kconfig.defconfig file.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Add a check to avoid invalidating the cache when the latter is disabled.
Indeed, doing so can lead to a bus fault.
Signed-off-by: Thomas Altenbach <taltenbach@witekio.com>
