drivers: can: stm32fd: rename CONFIG_CAN_STM32_CLOCK_DIVISOR
Rename CONFIG_CAN_STM32_CLOCK_DIVISOR to CONFIG_CAN_STM32FD_CLOCK_DIVISOR to match driver Kconfig name. Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
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322b436b30
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45d4909024
2 changed files with 14 additions and 8 deletions
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@ -52,8 +52,9 @@ config CAN_STM32FD_CLOCK_SOURCE_PCLK1
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endchoice
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config CAN_STM32_CLOCK_DIVISOR
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config CAN_STM32FD_CLOCK_DIVISOR
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int "CAN clock divisor"
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depends on CAN_STM32FD_CLOCK_SOURCE_PCLK1
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range 1 30
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default 1
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help
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@ -62,4 +63,4 @@ config CAN_STM32_CLOCK_DIVISOR
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Note that the the divisor affects all CAN controllers.
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Allowed values: 1 or 2 * n, where n <= 15.
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endif #CAN_STM32FD
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endif # CAN_STM32FD
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@ -26,10 +26,15 @@ LOG_MODULE_REGISTER(can_stm32fd, CONFIG_CAN_LOG_LEVEL);
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#error "Unsupported FDCAN clock source"
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#endif
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#if CONFIG_CAN_STM32_CLOCK_DIVISOR != 1 && CONFIG_CAN_STM32_CLOCK_DIVISOR & 0x01
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#error CAN_STM32_CLOCK_DIVISOR invalid.\
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Allowed values are 1 or 2 * n, where n <= 15
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#endif
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#ifdef CONFIG_CAN_STM32FD_CLOCK_DIVISOR
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#if CONFIG_CAN_STM32FD_CLOCK_DIVISOR != 1 && CONFIG_CAN_STM32FD_CLOCK_DIVISOR & 0x01
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#error CAN_STM32FD_CLOCK_DIVISOR invalid. Allowed values are 1 or 2 * n, where n <= 15.
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#else
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#define CAN_STM32FD_CLOCK_DIVISOR CONFIG_CAN_STM32FD_CLOCK_DIVISOR
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#endif /* CONFIG_CAN_STM32FD_CLOCK_DIVISOR */
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#else
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#define CAN_STM32FD_CLOCK_DIVISOR 1U
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#endif /* CONFIG_CAN_STM32FD_CLOCK_DIVISOR*/
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#define DT_DRV_COMPAT st_stm32_fdcan
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@ -43,7 +48,7 @@ static int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate)
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return -EIO;
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}
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*rate = rate_tmp / CONFIG_CAN_STM32_CLOCK_DIVISOR;
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*rate = rate_tmp / CAN_STM32FD_CLOCK_DIVISOR;
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return 0;
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}
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@ -53,7 +58,7 @@ static void can_stm32fd_clock_enable(void)
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LL_RCC_SetFDCANClockSource(CAN_STM32FD_CLOCK_SOURCE);
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__HAL_RCC_FDCAN_CLK_ENABLE();
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FDCAN_CONFIG->CKDIV = CONFIG_CAN_STM32_CLOCK_DIVISOR >> 1;
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FDCAN_CONFIG->CKDIV = CAN_STM32FD_CLOCK_DIVISOR >> 1;
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}
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static void can_stm32fd_set_state_change_callback(const struct device *dev,
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