drivers/clock_control: stm32u5: Move clock init to a single function
Move fixed clocks initialization to a single function. Benefit is they could now be enabled independently of the main clock configuration based on dts status and then be used by peripherals even is not part of the main clock tree. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou
Carles Cufí
parent
30b3a5ffe7
commit
ebb1d79e8f
1 changed files with 117 additions and 87 deletions
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@ -43,39 +43,6 @@ static void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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}
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#endif /* STM32_SYSCLK_SRC_PLL */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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/* Enable the power interface clock */
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
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if (IS_ENABLED(STM32_LSE_ENABLED)) {
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if (!LL_PWR_IsEnabledBkUpAccess()) {
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/* Enable write access to Backup domain */
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LL_PWR_EnableBkUpAccess();
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while (!LL_PWR_IsEnabledBkUpAccess()) {
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/* Wait for Backup domain access */
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}
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}
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/* Enable LSE Oscillator */
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LL_RCC_LSE_Enable();
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/* Wait for LSE ready */
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while (!LL_RCC_LSE_IsReady()) {
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}
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/* Enable LSESYS additionally */
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LL_RCC_LSE_EnablePropagation();
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/* Wait till LSESYS is ready */
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while (!LL_RCC_LSESYS_IsReady()) {
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}
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LL_PWR_DisableBkUpAccess();
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}
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}
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/**
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* @brief fill in AHB/APB buses configuration structure
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*/
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@ -246,45 +213,12 @@ static void set_regu_voltage(uint32_t hclk_freq)
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__unused
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static void clock_switch_to_hsi(uint32_t ahb_prescaler)
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{
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/* Enable HSI if not enabled */
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if (LL_RCC_HSI_IsReady() != 1) {
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/* Enable HSI */
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LL_RCC_HSI_Enable();
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while (LL_RCC_HSI_IsReady() != 1) {
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/* Wait for HSI ready */
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}
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}
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/* Set HSI as SYSCLCK source */
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
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}
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}
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static void set_up_clk_msis(void)
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{
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#if defined(STM32_SYSCLK_SRC_MSIS) || defined(STM32_PLL_SRC_MSIS)
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/* Set MSIS Range */
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LL_RCC_MSI_EnableRangeSelection();
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LL_RCC_MSIS_SetRange(STM32_MSIS_RANGE << RCC_ICSCR1_MSISRANGE_Pos);
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if (IS_ENABLED(STM32_MSIS_PLL_MODE)) {
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BUILD_ASSERT(STM32_LSE_ENABLED,
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"MSI Hardware auto calibration needs LSE clock activation");
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/* Enable MSI hardware auto calibration */
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LL_RCC_MSI_EnablePLLMode();
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}
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/* Set MSIS Range */
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LL_RCC_MSIS_Enable();
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/* Wait till MSIS is ready */
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while (LL_RCC_MSIS_IsReady() != 1) {
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}
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#endif /* STM32_SYSCLK_SRC_MSIS || STM32_PLL_SRC_MSIS */
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}
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/*
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* Configure PLL as source of SYSCLK
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@ -315,7 +249,6 @@ void config_src_sysclk_pll(LL_UTILS_ClkInitTypeDef s_ClkInitStruct)
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}
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if (IS_ENABLED(STM32_PLL_SRC_MSIS)) {
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set_up_clk_msis();
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/* Switch to PLL with MSI as clock source */
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LL_PLL_ConfigSystemClock_MSI(&s_PLLInitStruct, &s_ClkInitStruct);
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@ -349,22 +282,6 @@ void config_src_sysclk_hse(LL_UTILS_ClkInitTypeDef s_ClkInitStruct)
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{
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#ifdef STM32_SYSCLK_SRC_HSE
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/* Enable HSE if not enabled */
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if (LL_RCC_HSE_IsReady() != 1) {
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/* Check if need to enable HSE bypass feature or not */
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if (IS_ENABLED(STM32_HSE_BYPASS)) {
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LL_RCC_HSE_EnableBypass();
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} else {
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LL_RCC_HSE_DisableBypass();
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}
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/* Enable HSE */
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LL_RCC_HSE_Enable();
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while (LL_RCC_HSE_IsReady() != 1) {
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/* Wait for HSE ready */
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}
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}
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/* Set HSE as SYSCLCK source */
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
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@ -381,7 +298,6 @@ void config_src_sysclk_msis(LL_UTILS_ClkInitTypeDef s_ClkInitStruct)
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#ifdef STM32_SYSCLK_SRC_MSIS
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/* Set MSIS as SYSCLCK source */
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set_up_clk_msis();
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSIS);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSIS) {
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}
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@ -401,6 +317,120 @@ void config_src_sysclk_hsi(LL_UTILS_ClkInitTypeDef s_ClkInitStruct)
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#endif /* STM32_SYSCLK_SRC_HSI */
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}
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static void set_up_fixed_clock_sources(void)
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{
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if (IS_ENABLED(STM32_HSE_ENABLED)) {
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/* Check if need to enable HSE bypass feature or not */
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if (IS_ENABLED(STM32_HSE_BYPASS)) {
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LL_RCC_HSE_EnableBypass();
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} else {
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LL_RCC_HSE_DisableBypass();
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}
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/* Enable HSE */
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LL_RCC_HSE_Enable();
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while (LL_RCC_HSE_IsReady() != 1) {
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/* Wait for HSE ready */
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}
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}
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if (IS_ENABLED(STM32_HSI_ENABLED)) {
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/* Enable HSI if not enabled */
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if (LL_RCC_HSI_IsReady() != 1) {
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/* Enable HSI */
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LL_RCC_HSI_Enable();
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while (LL_RCC_HSI_IsReady() != 1) {
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/* Wait for HSI ready */
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}
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}
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}
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if (IS_ENABLED(STM32_LSE_ENABLED)) {
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/* Enable the power interface clock */
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LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PWR);
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if (!LL_PWR_IsEnabledBkUpAccess()) {
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/* Enable write access to Backup domain */
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LL_PWR_EnableBkUpAccess();
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while (!LL_PWR_IsEnabledBkUpAccess()) {
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/* Wait for Backup domain access */
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}
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}
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/* Enable LSE Oscillator */
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LL_RCC_LSE_Enable();
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/* Wait for LSE ready */
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while (!LL_RCC_LSE_IsReady()) {
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}
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/* Enable LSESYS additionnally */
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LL_RCC_LSE_EnablePropagation();
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/* Wait till LSESYS is ready */
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while (!LL_RCC_LSESYS_IsReady()) {
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}
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LL_PWR_DisableBkUpAccess();
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}
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if (IS_ENABLED(STM32_MSIS_ENABLED)) {
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/* Set MSIS Range */
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LL_RCC_MSI_EnableRangeSelection();
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LL_RCC_MSIS_SetRange(STM32_MSIS_RANGE << RCC_ICSCR1_MSISRANGE_Pos);
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if (IS_ENABLED(STM32_MSIS_PLL_MODE)) {
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__ASSERT(STM32_LSE_ENABLED,
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"MSIS Hardware auto calibration needs LSE clock activation");
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/* Enable MSI hardware auto calibration */
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LL_RCC_SetMSIPLLMode(LL_RCC_PLLMODE_MSIS);
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LL_RCC_MSI_EnablePLLMode();
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}
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/* Enable MSIS */
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LL_RCC_MSIS_Enable();
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/* Wait till MSIS is ready */
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while (LL_RCC_MSIS_IsReady() != 1) {
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}
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}
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if (IS_ENABLED(STM32_MSIK_ENABLED)) {
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/* Set MSIK Range */
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LL_RCC_MSI_EnableRangeSelection();
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LL_RCC_MSIK_SetRange(STM32_MSIK_RANGE << RCC_ICSCR1_MSIKRANGE_Pos);
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if (IS_ENABLED(STM32_MSIK_PLL_MODE)) {
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__ASSERT(STM32_LSE_ENABLED,
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"MSIK Hardware auto calibration needs LSE clock activation");
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/* Enable MSI hardware auto calibration */
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LL_RCC_SetMSIPLLMode(LL_RCC_PLLMODE_MSIK);
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LL_RCC_MSI_EnablePLLMode();
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}
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if (IS_ENABLED(STM32_MSIS_ENABLED)) {
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__ASSERT((STM32_MSIK_PLL_MODE == STM32_MSIS_PLL_MODE),
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"Please check MSIS/MSIK config consistency");
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}
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/* Enable MSIK */
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LL_RCC_MSIK_Enable();
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/* Wait till MSIK is ready */
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while (LL_RCC_MSIK_IsReady() != 1) {
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}
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}
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if (IS_ENABLED(STM32_LSI_ENABLED)) {
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/* Enable LSI oscillator */
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LL_RCC_LSI_Enable();
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while (LL_RCC_LSI_IsReady() != 1) {
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}
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}
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}
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int stm32_clock_control_init(const struct device *dev)
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{
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uint32_t old_hclk_freq = 0;
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@ -411,6 +441,9 @@ int stm32_clock_control_init(const struct device *dev)
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/* configure clock for AHB/APB buses */
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config_bus_clk_init((LL_UTILS_ClkInitTypeDef *)&s_ClkInitStruct);
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/* Set up indiviual enabled clocks */
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set_up_fixed_clock_sources();
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/* Set voltage regulator to comply with targeted system frequency */
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set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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@ -423,9 +456,6 @@ int stm32_clock_control_init(const struct device *dev)
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LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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}
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/* Some clocks would be activated by default */
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config_enable_default_clocks();
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/* Set peripheral busses prescalers */
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LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_AHB_PRESCALER));
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LL_RCC_SetAPB1Prescaler(apb1_prescaler(STM32_APB1_PRESCALER));
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