drivers: can: stm32fd: add clock source selection
Add support for selecting the CAN clock source. Change previously hardcoded value of PCLK1 to HSE. Fixes: #44985 Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
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2 changed files with 34 additions and 1 deletions
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@ -29,6 +29,29 @@ config CAN_MAX_EXT_ID_FILTER
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Defines the maximum number of filters with extended ID (29-bit)
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that can be attached.
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choice CAN_STM32FD_CLOCK_SOURCE
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prompt "CAN clock source"
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default CAN_STM32FD_CLOCK_SOURCE_HSE
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help
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CAN clock source selection.
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config CAN_STM32FD_CLOCK_SOURCE_HSE
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bool "HSE"
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help
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HSE clock used as FDCAN clock source.
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config CAN_STM32FD_CLOCK_SOURCE_PLL
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bool "PLL"
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help
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PLL "Q" clock used ad FDCAN clock source.
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config CAN_STM32FD_CLOCK_SOURCE_PCLK1
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bool "PCLK1"
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help
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PCLK1 clock used ad FDCAN clock source.
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endchoice
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config CAN_STM32_CLOCK_DIVISOR
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int "CAN clock divisor"
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range 1 30
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@ -16,6 +16,16 @@
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LOG_MODULE_REGISTER(can_stm32fd, CONFIG_CAN_LOG_LEVEL);
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#if defined(CONFIG_CAN_STM32FD_CLOCK_SOURCE_HSE)
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#define CAN_STM32FD_CLOCK_SOURCE LL_RCC_FDCAN_CLKSOURCE_HSE
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#elif defined(CONFIG_CAN_STM32FD_CLOCK_SOURCE_PLL)
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#define CAN_STM32FD_CLOCK_SOURCE LL_RCC_FDCAN_CLKSOURCE_PLL
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#elif defined(CONFIG_CAN_STM32FD_CLOCK_SOURCE_PCLK1)
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#define CAN_STM32FD_CLOCK_SOURCE LL_RCC_FDCAN_CLKSOURCE_PCLK1
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#else
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#error "Unsupported FDCAN clock source"
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#endif
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#if CONFIG_CAN_STM32_CLOCK_DIVISOR != 1 && CONFIG_CAN_STM32_CLOCK_DIVISOR & 0x01
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#error CAN_STM32_CLOCK_DIVISOR invalid.\
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Allowed values are 1 or 2 * n, where n <= 15
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@ -40,7 +50,7 @@ static int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate)
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static void can_stm32fd_clock_enable(void)
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{
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LL_RCC_SetFDCANClockSource(LL_RCC_FDCAN_CLKSOURCE_PCLK1);
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LL_RCC_SetFDCANClockSource(CAN_STM32FD_CLOCK_SOURCE);
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__HAL_RCC_FDCAN_CLK_ENABLE();
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FDCAN_CONFIG->CKDIV = CONFIG_CAN_STM32_CLOCK_DIVISOR >> 1;
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