This patch will set MMU permissions for rom_ext sections
It is possible to call the rom_ext code located in IMR
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
This patch will extend MMU mapping range for hwreg1 entry
because it is required to access lower register addresses
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
nrf54h20 device requires device runtime PM to be enabled when
device PM is in use.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Current code configures the higher bits ahead of drive strength
to be "1", this patch fix this issue.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Lei Xu <lei.xu@nxp.com>
Updated `CMakeLists.txt` and `Kconfig` to integrate power management
for RA8D1, RA8M1, and RA8T1.
Modified `Kconfig.defconfig` to configure ULPT timer as the system timer
when power management is enabled:
- Adjusted `SYS_CLOCK_HW_CYCLES_PER_SEC` and `SYS_CLOCK_TICKS_PER_SEC`
for ULPT timer.
- Disabled `CORTEX_M_SYSTICK` when ULPT timer is used as the system timer.
Implemented power management logic in the new `power.c` file for:
- RA8D1 (`soc/renesas/ra/ra8d1/power.c`)
- RA8M1 (`soc/renesas/ra/ra8m1/power.c`)
- RA8T1 (`soc/renesas/ra/ra8t1/power.c`)
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/T2M
Corrected space in the comment.
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
Renesas takes over the maintainer of SoC Renesas RZ/T2M to unify with
other RZ devices
- Move soc/renesas/rzt2m to soc/renesas/rz
- Support xSPI boot mode to boot code from flash
- Change to use HAL Renesas
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
RAM power configuration is preserved through soft reset,
meaning that there is a risk of accessing powered off RAM blocks
when booting in different application (i.e. bootloader).
Add option to force all RAM blocks to be powered on
before triggering soft reset to prevent this from happening.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
The chip requires a successful sleep entry to change the PLL sequence.
By default, the IT8XXX2 chip enables the I2C0 alternate function, which
can cause the clock/data lines to meet the start condition, preventing
EC from entering sleep mode.
This commit disables the I2C0 alternate function before executing the
PLL sequence change to ensure that the EC can enter sleep mode
successfully.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
STM32F439 SoC is an STM32F429 with an integrated crypto/hash processor
providing hardware acceleration for encryption (AES and TDES) and hash
(MD5, SHA-1 and SHA-2).
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Convert z_clock_hw_cycles_per_sec to unsigned int to increase
supported frequency range.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
This is the initial commit to support pinctrl driver for Renesas RZ/V2L
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Add support for the RPU, real-time processing unit on Versal NET SoC.
It is based on Cortext-R52 processor.
The patch contains initial wiring and configuration for generic board
with OCM(1MB) and DDR(2G) memories, cpu, interrupt controller, global
timer and UART.
versalnet.dtsi contains common peripherals integrated into Versal NET
SoC, and versalnet_r52.dtsi has peripherals which are private to
Cortex-R52 processor.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Signed-off-by: Mubin Sayyed <mubin.sayyed@amd.com>
Check if the option bits DT nodes are enabled before including them in
the linker script for all RA SoCs. These must be disabled for targets
that provide a separate bootloader.
This commit adds the DT_NODE_HAS_STATUS_OKAY gates to all RA-series SoC
linker scripts, converting existing ones to the new macro.
The changes in this commit have been mechanically generated using find
and awk tools.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
- Add new device tree source include file for DA14697 SoC
- Update Kconfig and soc.yml to support the new device
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
if CONFIG_PM=y, board will enter low power,
which will cause problem for debugger.
So for ztest cases, we need enable this to avoid problem.
This used to apply to soc/platform level, now remove them.
Signed-off-by: Hake Huang <hake.huang@nxp.com>
Add .resource_table section to the linker script for the
i.MX95. This section is used by intercore communication to
publish features and configurations to the remote
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
Enable support for using an external clock as the main clock.
When bypass mode is enabled, the external crystal oscillator is bypassed,
and the main clock is directly driven by an external clock signal.
Signed-off-by: Perry Hung <perry@mosi.io>
It is defined as spis120 rather than spi120,
because spi120 is already used for SPIM120 hardware instance,
but their base address is different.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Add ULP Coprocessor board support for C6.
This requires a change in the board qualifier depending on the build
target.
Update esp32c6 overlay and configuration files to the proper name.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
This maps to Zephyr power state Standby. In this power
state the OS Timer cannot be used as a wakeup source as
it will be powered off. Hence the counter is enabled
and RTC is used to keep track of system ticks and wakeup
the system.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Since the clock source when running in PM mode 3 is the
slower 1KHx clock, we adjust the SYS_CLOCK_TICKS_PER_SEC
value to get better accuracy.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This clock is used for certain peripherals such
as RTC.
On certain RW612 boards such as rd_rw612_bga, XTAL32K
and ENET share pins. Add code to check if ENET and
XTAL32 are enabled at the same time.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
