Protection circuit must be disabled to use NFCT antenna pins
as GPIOs. It can be done by adding nfct-pins-as-gpios to nfct
node in the devicetree in cpuapp. Node must be disabled as
NFCT is not used. In legacy platforms same property was added
to uicr node because that information was stored in UICR. In
nrf54h20 it is not part of UICR so property is part of nfct
node.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add initial support for nuvoton numaker m55m1x SoC series
including basic init and device tree source include.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
VPR (FLPR) on nRF54L series has fixed issue with sleeping so
custom CPU idle function does not need to be used there.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add support for the Octavo's OSD32MP1-BRK platform. The board uses
Octavo's OSD32MP15x SiP which integrates STM32MP157F MCU and
its SoC configuration.
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
MD5 and SHA1 are not supposed to be used nowadays on security context.
Some ancillary scripts in tree do use them, but for verification only -
or where externally mandated, such the SPDX tool.
This patch marks those usages as `usedforsecurity=False`, which helps
clarify intent.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Update the NEORV32 SoC, peripheral drivers, and board to support NEORV32
v1.11.1. Notable changes include:
- Optional RISC-V ISA Kconfigs are now selected on the board level.
- Peripheral registers are now automatically reset in hardware, no need for
software initialization code.
- The NEORV32 GPIO controller now supports 32 pins, not 64. Interrupt
support will be submitted in a separate PR.
- Default board configuration has 64k RAM and is clocked at 18 MHz.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Originally, when Zephyr support for the NEORV32 was introduced, the idea
was to support multiple version of the SoC in Zephyr as development on the
open-source RISC-V processor continued.
Unfortunately, this has proven to be much harder than anticipated in part
due to incompatible changes between NEORV32 versions and part due to the
added test burden of verifying all changes on many different versions and
configurations.
Going forward, Zephyr will support a given release of the NEORV32
processor.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
The NEORV32 v1.8.6 does not fully support the RISC-V ISA A
extension. Remove it and enable support for atomic operations in C
regardless of the version used.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This changes make PM state setting functions in SOC level weak so they
can be overridden by board/app level.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Currently, the soc/stm32/ccm.ld is not handled in
CMAKE_LINKER_GENERATOR.
This commit adds support, making STM32 supportable by
alternative linkers such as AC6 and IAR.
This commit also renames a variable to match all other
LOADADDR symbols.
Signed-off-by: Robin Kastberg <robin.kastberg@iar.com>
Move macro from nrf_clock_control.h to soc_nrf_common.h. Clock control
header fetches many dependencies (e.g. onoff.h) so move macro to more
low level header.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Include configuration file for cases when this file is complied
in special builds (e.g. TFM).
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Added CONFIG_AMBIQ_COMPONENT_USE_BT and CONFIG_SOC_AMBIQ_BT_SUPPORTED
to fix empty zephyr_library() warning when BLE is not needed for compile.
Added CMake message if BT related Ambiq specific Kconfig is overriden for
not supported SoC.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
The i.MX RT700 has an ultra-low power Sense Subsystem
which includes an ARM Cortex-M33 and
Cadence Tensilica HiFi 1 DSP.
Here, we add support for the HiFi1 core.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
The i.MX RT700 has a compute subsystem which includes
a primary ARM Cortex-M33 running at 325 MHz and
Cadence Tensilica HiFi4 DSP.
Here, we add support for the HiFi4 core.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Current interrupt allocator is not taking into account
reserved areas. In case of esp32c6, Wi-Fi isn't properly
configured, causing instability or even non-functional feature.
This adds the reserved area ranges for all risc-v based SoC and
unify the slot finding based on interrupt source.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Make sure QIO mode calls are not in flash, otherwise
it will fail during bootloader/flash init.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Make sure chip revision reading returns real value
for some especific chip revision, which is currently
failing.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The lowest bit in DSE and FSEL field of pinctl register is not used
in the register and dts binding definitions also don't conver this bit,
so shift one more bit to align with actual register definitions.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Add conditional compilation check for swj_connector_init call in
soc_early_init_hook to prevent link errors when swj_port is disabled
in device tree. The code is now wrapped with
DT_NODE_HAS_STATUS_OKAY(SWJ_NODE) to ensure the function is only
included when the corresponding device tree node is enabled.
This fixes the undefined reference link error that occurs when
compiling with swj_port disabled in the device tree configuration.
Signed-off-by: Jhan BoChao <jhan_bo_chao@realtek.com>
This driver was deprecated and must be removed by Zephyr version
4.1 according to lifecycle/release guidelines.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This config was missed when converting from eth_mcux to nxp_enet driver,
re-add it and use new one instead of old one.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Drop the override conditions to ADC_MCUX_12B1MSPS_SAR for imxrt, the
current one causes the driver to be built when it does not have to and
are not needed anyway, and drop the HAS_MCUX_12B1MSPS_SAR option
entirely as it's not needed anymore.
Tested with:
west build -p -b teensy40 tests/lib/devicetree/api_ext
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
When DEBUG_OPTIMIZATION or NO_OPTIMIZATION is
enabled, efuse reading fails during bootloader start.
Move those calls into IRAM area so that reading when
cache is disabled works without any faults.
In HAL side, we need to use low level calls to read
CPU id instead of Zephyr's default one.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Fixing multiple things related to psram usage:
- fix conflicting psram0 dts node for all ESP32 SiP and SoC.
- fix dcache and icache area used in psram mapping.
- fix smh spiram heap allocations.
- add `espressif,esp32-psram` compatible to set psram0 size in dts.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
If a board defined CONFIG_FLASH_LOAD_OFFSET to a non-zero value,
enabling CONFIG_SOC_IT8XXX2_JTAG_DEBUG_INTERFACE generated a linker
error because when trying to move the location counter backwards.
Fixed by allocating the JTAG section within the deined ROM region.
Signed-off-by: Keith Short <keithshort@google.com>
This commits repairs calling function trdc_enable_all_access() only
when using build for standalone CM33 or CM7 core build.
For the multicore this function should be called only by CM33 core.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
After updating the main_clk, need to update the frequency tracked in
HAL MCUXpresso SDK framework for other drivers.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Enabling Dcache on RA8D1 will cause many issue with data coherence
in driver.
This commit disable Dcache for RA8D1 as temporary solution, user
can enable it but should be aware of data coherence issue
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
PM, PM_DEVICE etc should be enabled by the application/samples, not the
board.
Add a config to default to custom policy for the board though since
there's one defined at soc level.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
- Move config BUILD_OUTPUT_HEX and CLOK_CONTROL from board deconfig
into SoC deconfig
- Add clock-frequency in dts to get config
SYS_CLOCK_HW_CYCLES_PER_SEC from dts
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Add a Kconfig option ESPI_NPCX_RESET_SLP_SX_VW_ON_ESPI_RST.
When the option is enabled, the hardware resets the SLP_S3/SLP_S4/SLP_S5
virtual wires when the eSPI_Reset is asserted. This is required to
synchronize these virtual wires on the ungraceful global reset.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
