If a board defined CONFIG_FLASH_LOAD_OFFSET to a non-zero value,
enabling CONFIG_SOC_IT8XXX2_JTAG_DEBUG_INTERFACE generated a linker
error because when trying to move the location counter backwards.
Fixed by allocating the JTAG section within the deined ROM region.
Signed-off-by: Keith Short <keithshort@google.com>
This commits repairs calling function trdc_enable_all_access() only
when using build for standalone CM33 or CM7 core build.
For the multicore this function should be called only by CM33 core.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
After updating the main_clk, need to update the frequency tracked in
HAL MCUXpresso SDK framework for other drivers.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Enabling Dcache on RA8D1 will cause many issue with data coherence
in driver.
This commit disable Dcache for RA8D1 as temporary solution, user
can enable it but should be aware of data coherence issue
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
PM, PM_DEVICE etc should be enabled by the application/samples, not the
board.
Add a config to default to custom policy for the board though since
there's one defined at soc level.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
- Move config BUILD_OUTPUT_HEX and CLOK_CONTROL from board deconfig
into SoC deconfig
- Add clock-frequency in dts to get config
SYS_CLOCK_HW_CYCLES_PER_SEC from dts
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
Add a Kconfig option ESPI_NPCX_RESET_SLP_SX_VW_ON_ESPI_RST.
When the option is enabled, the hardware resets the SLP_S3/SLP_S4/SLP_S5
virtual wires when the eSPI_Reset is asserted. This is required to
synchronize these virtual wires on the ungraceful global reset.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commit adds MBOX device tree entry for RT1180.
Adds functions to copy and boot CM7 core.
Adds MPU region for shared memory without caching.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
As a result of flash initialization improvements
and fixes, some of the mcuboot linker entries
are no longer necessary.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Currently, each SoC has its own CMakeLists.txt file
to handle esp32 runner.
This PR merged it all in a common file and fixes
missing configuration such as flashing frequency,
mode and size.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Removes the VDDSDIO control during boot for some SoCs.
Only ESP32 allows managing such configuration during
initialization.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This change splits eth sram region name definition
and configuration.
In the end the configuration is stored only once
er declared name.
This name shall increase readability and maintainability
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
The current implementation requires SoCs/Boards to manualy instantiate
the preripherals and initilize them.
The change lets Zephyr rely on the device tree setup to instantiate &
initialize the relevant gpio peripheral.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
When TRDC permission fails to be obtained, it does not recycle to
access ELE core to prevent blocking problems. The current practice
only generates a log warning alarm.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Currently the resource table is added to the memory-region labeled DDR.
This region can also be extra space for code/data, although this is
not yet implemented. This will mean that the linker is free to put
the resource table *after* the code/data sections in DDR. The resource
table must be at the start of the assigned DRAM area for the remote
core to support early-boot/late-attach usecases.
To solve this, we carveout the first 4KB of our DRAM area specifically
for the resource table. This matches how this issue was solved for the
K3 R5F cores.
To make this clear we label this memory-region "RSC_TABLE". This is
done at the linker file level, which is common for all K3 M4 boards
and so we update all 3 such boards in this one patch instead of
patch-per-board.
Signed-off-by: Andrew Davis <afd@ti.com>
I think my original idea with this default MPU setup was that the top
bits of the (fast) SRAM region might be useful for host DMA that
needed better latencies than the (extremely slow) system DRAM
mappings. So it should be left uncached for safety.
But unfortunately the author[1] of the SOF heap integration for this
platform decided to size the heap dynamically to use most of the SRAM
block (the vectors and a few other bits live at the bottom, but most
of .text is in DRAM).
Needless to say, an uncached heap is sort of a performance disaster.
It worked OK for default copy-only topologies but fell over the moment
we turned on nontrivial processing.
[1] Um... Hi. Yeah, that's me too.
Signed-off-by: Andy Ross <andyross@google.com>
Recent Python interpreters have started tossing bus errors from this
12-byte string search (the loader is looking for the winstream
descriptor in the live firmware image). My guess is that there's a
SIMD optimization that's been added that's trying to do e.g. a 16 byte
load, and something in the fabric is kicking that out. Note that this
is 100% a software change: the same hardware with one version of the
host environment works, and an update breaks it.
But really I have no idea what's happening here, the memory region in
question is documented as system DRAM, the same bus regular process
memory is on (it's just not kernel-utilized memory). All I know is
that the bus error is introduced with a Python upgrade from 3.8.20 to
3.11.10.
Regardless, it's no great hardship to do the search on 64 bit chunks.
Signed-off-by: Andy Ross <andyross@google.com>
When TRDC permission fails to be obtained, it does not recycle to
access ELE core to prevent blocking problems. The current practice
only generates a log warning alarm.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
silabs_s2 uses simplicity_sdk hal library, which already have by default
a zero latency IRQs mechanism with a hardcoded value. In order to be
aligned with simplicity_sdk, we need to activate Zero Latency IRQ in
Zephyr by default. The level (2) depends on the hardcoded
value in simplicity_sdk (CORE_ATOMIC_BASE_PRIORITY_LEVEL). Without this
fix, if you use an IRQ with a priority of 0 or 1, irq_lock() and
irq_unlock() have no effect for this IRQ.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
This SoC has an external XCACHE controller for CPU0
instruction and data bus.
Add code to enable the data cache. Instruction cache
is already enabled by SystemInit.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Update to support APP_CPU flash access.
- fix the map_rom_segment so it can be used in other context
- add IROM and DROM region size in Kconfig
- update the memory.h by using dts records
- fix the appcpu ld file to support flash
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Update and enable Wi-Fi/Bluetooth software coexistence management.
This improves package handling and is recommended to be used
in high traffic scenarios.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Decouple dependency of CONFIG_NXP_WIFI_SOFTAP_SUPPORT.
Add wifi defconfig to set default kconfig options when soft AP
enabled.
Signed-off-by: Fengming Ye <frank.ye@nxp.com>
The i.MX 91 SoC’s integrated EdgeLock® Secure Enclave provides
security features including lifecycle management, tamper detection,
secure boot and a simplified path to certifications. The i.MX 91
family features an Arm® Cortex®-A55 running at up to 1.4GHz,
support for modern LPDDR4 memory to enable platform longevity,
dual Gigabit Ethernet and dual USB ports, along with a rich set
of peripherals targeting medical, industrial and consumer IoT
market segments.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
This driver allow to use Zephyr native IP stack or the IP stack provided
by HAL / WiseConnect.
The WiseConnect implementation may take advantage of the specific
features provided by the 917 (power consumption, speed,
validation...).
Some notable features are not available with this interface:
- It seems Zephyr does not provide API to offload multicast membership
management. User should be to directly call WiseConnect APIs
- Support for ICMP frames is difficult. Note that WiseConnect
automatically answer to ping request. It is just not possible to
send ping requests and receive ping responses.
- Zephyr and WiseConnect both support TLS offloading. However this
patch does not implement it.
- Reentrancy in the WiseConnect side is uncertain.
This implementation has been tested with samples/net/wifi/ (which relies
on subsys/net/lib/shell).
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Driver was tested with a custom application which enabled the BT_SHELL.
Basic functionalities were verified:
- Scanning
- Advertising
- Connecting
Configuration needed for the test:
- CONFIG_BT=y
- CONFIG_BT_PERIPHERAL=y
- CONFIG_BT_CENTRAL=y
- CONFIG_BT_SHELL=y
- CONFIG_SHELL=y
Co-authored-by: Tibor Laczko <tibor.laczko@silabs.com>
Signed-off-by: Tibor Laczko <tibor.laczko@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
