STM32_DT_CLOCKS was designed to take a device tree node label name as
argument: STM32_DT_CLOCKS(uart1)
Change its implementation to take a node identifier instead:
STM32_DT_CLOCKS(DT_NODELABEL(uart1)).
This make its usage more flexible since the argument can now be extracted
from other DT macros such as DT_PARENT. Then, the following can be done:
STM32_DT_CLOCKS(DT_PARENT(child_node_label)).
Since it is now possible implement STM32_DT_INST_CLOCKS using
STM32_DT_CLOCKS.
Finally, update existing STM32_DT_CLOCKS users and convert
STM32_INST_CLOCK_INFO users to STM32_CLOCK_INFO.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Simple driver that allows one to choose the clock speed of xtensa cores.
It's basically a shim layer on top of SOC level driver.
Also, a really simple test case was added, mainly to ensure things are
build and are sane.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Since implementation of clock source selection in consumer device drivers
could be achieved without usage of a clock-names property and no
example of usage is provided up to now, remove this property from existing
examples.
Additionally, make it clear in stm32 clock control binding that it is
driver's responsibility to correctly access clock source information
and use it as required.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a test section to enable device clock source selection testing.
Test targets I2C1 device which supports clock source selection
on all SOCs using this driver except L1
Initial test done on wb target.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Move stm32_common tests to stm32_common_core before adding new folder
for device source selection tests.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
PLL input should be between 4 and 16MHz, so when MSI is set to 4MHz
fix PLLM can't be higher than 1.
Fix PLL1-NQR in consequence.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a stm32u5_devices test which aims at testing devices
clock control configuration on stm32u5 targets
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Make use of STM32_DT_CLOCKS_ macros to have the test work conditionally
based on alt clock presence.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add 2 clocks tests around device clock configuration on stm32h7.
For now, 'spi1_pllq_2_d1ppre_4' test variant is failed, which
illustrates issue reported in #41650.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to bring consistency in-tree, migrate all tests to the new
prefix <zephyr/...>. Note that the conversion has been scripted, refer
to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Rework test_*_freq to test HCLK freq instead of SYSCLK one, as it is not
correct to compare CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC with SYSCLK.
Additionally, add a test to verify use of AHB prescaler.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of testing SysClockFreq setting, we should instead check HCLK
setting which is the real zephyr CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
counterpart (core clock freq) and takes AHB prescaler setting into
account.
Additionally, update one test configuration to explicitly verify AHB
prescaler is correctly taken into account by clock driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove L0 and L1 targets from "sysclksrc_msi_48" test case as this
MSI range 11 is not an allowed value on these series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Test doesn't do any check on prescalers. Remove references and
existing user: wx_clear_clocks overlay.
Proceed to new factorization when possible.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Since they don't have impact on sysclock src configuration,
remove LSI/E clocks from clear clocks overlays.
This enables the possibility to factorize wl and wb clear clocks overlays
and brings some use cases factorizations as well.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Revise test cases naming:
- Replace _<series>_ by a .<series>. field in test cases naming
- Rename clear_clocks_msi.overlay to clear_msi.overlay
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Fix selection of boards used:
- Remove superfluous/redundant configs
- Adapt to boards available on ST test bench
- fix typos
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
To be functional, harness_config require a `harness: ztest` property,
add it.
Additionally, provide a comment to explain motivation behind this fixture.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Before introducing a new test for peripheral clocks,
rename existing stm32h7 test section by stm32h7_core.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
target is stm32fxx with clearing clock config
target is stm32fxx with pll from hsi clock config
target is stm32fxx with pll from hse clock config (with bypass)
target is stm32fxx with hse, hsi, clock config (no pll)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
target is stm32l4x/l5x with clearing clock config
target is stm32l4x/l5x with pll 64MHz from hsi clock config
target is stm32l4x/l5x with pll 48MHz from msi clock config
target is stm32l4x/l5x with pll 64MHz from hse clock config (with bypass)
target is stm32l4x/l5x with hse, hsi, msi clock config (no pll)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Testing the HSE on the nucleo_stm32g071rb requires a hw fixture
on the hw board : MCO signal must given by the STLink to the mcu.
Put a hardware fixture to activate the hse clock with by-passed
only if the SB17 is closed on the HW.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
target is stm32wb55 with clearing clock config
target is stm32wb55 with pll 48MHz from hsi clock config
target is stm32wb55 with pll 48MHz from msi clock config
target is stm32wb55 with pll 64Hz from hse clock config
target is stm32wb55 with hse, msi, hsi clock config (no pll)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
target is stm32wl55 with clearing clock config
target is stm32wl55 with pll 48MHz from hsi clock config
target is stm32wl55 with pll 48MHz from hse clock config
target is stm32wl55 with hse clock config (no pll)
target is stm32wl55 with msi clock config (no pll)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fix build error for stm32 devices which have no function
to get the PLL ON bit from the RCC_CR register
Use the register access instead.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
target is stm32l1/l0 with pll 32MHz from hsi clock config
target is stm32l1/l0 with pll 32MHz from hse clock config
target is stm32l1/l0 with hse clock config (no pll)
target is stm32l1/l0 with hsi clock config (no pll)
target is stm32l1/l0 with msi clock config (no pll)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
target is stm32g4 with pll 64MHz from hsi clock config
target is stm32g4 with pll 64MHz from hse clock config
target is stm32g4 with hsi clock config (no pll)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
target is stm32g0 with pll 64MHz from hsi clock config
target is stm32g0 with pll 64MHz from hse clock config
target is stm32g0 with hsi clock config (no pll)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Use DEVICE_DT_GET to obtain a reference to the chosen entropy device.
The device is now global, and readiness is checked at the test setup
fixture.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
On nrf52832 disabling low frequency clock results in RTC COUNTER
reset. It is unexpected and system clock can be disrupted and
test may hang. Disable test which restarts LF clock for nrf52832.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
On nrf52832 LF clock cannot be stopped during runtime because
it resets RTC COUNTER. Testsuite run on nrf clock control driver
assumes that it will not happen. Disabling testing of LF clock
for nrf52832.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
To ease maintenance, add a common section.
It appears that using DTC_OVERLAY_FILE in the common section
preserves the required overlay order.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of relying on default board configuration,
add a specific test for this config.
Additionally rename existing pll_msi_80 to pll_msis_160.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of relying on existing board clock configuration,
use a clear_clocks.overlay file to first reset the clock
configuration to the default .dtsi state, then apply a
new configuration.
This method should be more robust when trying to use on more
boards and has the benefit to provide correct configuration
examples.
This relies on the fact that overlays are applied in the order
they are provided in DTC_OVERLAY_FILE CMake variable.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add a test suite to check various clocks configurations.
Test is based on HAL functions that read clock configuration
from registers.
One test is build only, as there is no available hw to test it today.
Others can be tested on target.
More configurations and test points could be added in future.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Convert remaining tests and samples to using find_package() instead of
literally including the CMake boilerplate code.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Move to CMake 3.20.0.
At the Toolchain WG it was decided to move to CMake 3.20.0.
The main reason for increasing CMake version is better toolchain
support.
Better toolchain support is added in the following CMake versions:
- armclang, CMake 3.15
- Intel oneAPI, CMake 3.20
- IAR, CMake 3.15 and 3.20
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
