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tests: drivers: stm32 clock control testing on stm32g4

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target is stm32g4 with pll 64MHz from hsi clock config
target is stm32g4 with pll 64MHz from hse clock config
target is stm32g4 with hsi clock config (no pll)

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2022-02-25 15:12:59 +01:00 • committed by Maureen Helm
commit 032fb610a4
3 changed files with 57 additions and 2 deletions
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20
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/hse_24.overlay Normal file
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@ -0,0 +1,20 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
clock-frequency = <DT_FREQ_M(24)>; /* 24MHz clock */
status = "okay";
};
&rcc {
clocks = <&clk_hse>;
clock-frequency = <DT_FREQ_M(24)>;
};

30
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_170_hse_24.overlay Normal file
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@ -0,0 +1,30 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
clock-frequency = <DT_FREQ_M(24)>;
status = "okay";
};
&pll {
div-m = <6>;
mul-n = <85>;
div-p = <7>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(170)>;
};

9
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml
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@ -1,13 +1,18 @@
common:
timeout: 5
platform_exclude: nucleo_h723zg b_u585i_iot02a
tests:
drivers.stm32_clock_configuration.common.sysclksrc_pll_64_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_64_hse_8.overlay"
platform_allow: nucleo_g071rb
drivers.stm32_clock_configuration.common.sysclksrc_pll_64_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_64_hsi_16.overlay"
platform_allow: nucleo_g071rb
platform_allow: nucleo_g071rb nucleo_g474re
drivers.stm32_clock_configuration.common.sysclksrc_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
platform_allow: nucleo_g071rb
drivers.stm32_clock_configuration.common.sysclksrc_hse_24:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_24.overlay"
platform_allow: nucleo_g474re
drivers.stm32_clock_configuration.common.sysclksrc_pll_170_hse_24:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
platform_allow: nucleo_g474re