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tests/drivers/clock_control: stm32h7: Add test for devices clock cfg

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Add 2 clocks tests around device clock configuration on stm32h7.
For now, 'spi1_pllq_2_d1ppre_4' test variant is failed, which
illustrates issue reported in #41650.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-01-13 17:23:55 +01:00 • committed by Carles Cufí
commit 78f40773b8
8 changed files with 313 additions and 0 deletions
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9
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/CMakeLists.txt Normal file
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# SPDX-License-Identifier: Apache-2.0
cmake_minimum_required(VERSION 3.20.0)
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(stm32_clock_configuration_h7_devices)
FILE(GLOB app_sources src/*.c)
target_sources(app PRIVATE ${app_sources})

106
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/core_init.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay clears clocks back to a state equivalent to what could
* be found in stm32h7.dtsi
*/
/* Clocks clean up config
* Aim is to avoid conflict with specific default board configuration
*/
&clk_hse {
status = "disabled";
/delete-property/ hse-bypass;
/delete-property/ clock-frequency;
};
&clk_hsi {
status = "disabled";
/delete-property/ hsi-div;
};
&clk_csi {
status = "disabled";
};
&clk_lse {
status = "disabled";
};
&clk_lsi {
status = "disabled";
};
&pll {
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-p;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
status = "disabled";
};
&pll3 {
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-p;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
status = "disabled";
};
&rcc {
/delete-property/ clocks;
/delete-property/ clock-frequency;
/delete-property/ d1cpre;
/delete-property/ hpre;
/delete-property/ d1ppre;
/delete-property/ d2ppre1;
/delete-property/ d2ppre2;
/delete-property/ d3ppre;
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>;
pinctrl-names = "default";
status = "disabled";
};
/* Core set up
* Aim of this part is to provide a base working clock config
*/
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <24>;
div-p = <2>;
div-q = <1>;
div-r = <1>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(96)>;
d1cpre = <1>;
hpre = <1>;
d1ppre = <1>;
d2ppre1 = <1>;
d2ppre2 = <1>;
d3ppre = <1>;
};

31
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pll3p_1_d1ppre_4.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after core_init.overlay file.
*/
&pll3 {
clocks = <&clk_hse>;
div-m = <1>;
mul-n = <24>;
div-p = <1>;
status = "okay";
};
&rcc {
/delete-property/ d1ppre;
d1ppre = <4>;
};
&spi1 {
/delete-property/ clocks;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
<&rcc STM32_SRC_PLL3_P SPI123_SEL(2)>;
clock-names = "reg", "kernel";
status = "okay";
};

28
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pllq_1_d1ppre_1.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after core_init.overlay file.
*/
&pll {
/delete-property/ div-q;
div-q = <1>;
};
&rcc {
/delete-property/ d1ppre;
d1ppre = <1>;
};
&spi1 {
/delete-property/ clocks;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
<&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
clock-names = "reg", "kernel";
status = "okay";
};

28
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_pllq_2_d1ppre_4.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after core_init.overlay file.
*/
&pll {
/delete-property/ div-q;
div-q = <2>;
};
&rcc {
/delete-property/ d1ppre;
d1ppre = <4>;
};
&spi1 {
/delete-property/ clocks;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
<&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>;
clock-names = "reg", "kernel";
status = "okay";
};

1
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/prj.conf Normal file
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CONFIG_ZTEST=y

100
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/test_stm32_clock_configuration.c Normal file
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/*
* Copyright (c) 2022 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <ztest.h>
#include <soc.h>
#include <drivers/clock_control.h>
#include <drivers/clock_control/stm32_clock_control.h>
#include <logging/log.h>
LOG_MODULE_REGISTER(test);
/* Not device related, but keep it to ensure core clock config is correct */
static void test_sysclk_freq(void)
{
uint32_t soc_sys_clk_freq;
soc_sys_clk_freq = HAL_RCC_GetSysClockFreq();
zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq,
"Expected sysclockfreq: %d. Actual sysclockfreq: %d",
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq);
}
static void test_spi_clk_config(void)
{
struct stm32_pclken spi1_reg_clk_cfg = {
.enr = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(spi1), reg, bits),
.bus = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(spi1), reg, bus)
};
struct stm32_pclken spi1_ker_clk_cfg = {
.enr = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(spi1), kernel, bits),
.bus = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(spi1), kernel, bus)
};
uint32_t spi1_actual_clk_src, spi1_dt_ker_clk_src;
uint32_t spi1_dt_clk_freq, spi1_actual_clk_freq;
int r;
/* Test clock_on(reg_clk) */
r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &spi1_reg_clk_cfg);
zassert_true((r == 0), "Could not enable SPI reg_clk");
zassert_true(__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 reg_clk should be on");
TC_PRINT("SPI1 reg_clk on\n");
/* Test clock_on(ker_clk) */
r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &spi1_ker_clk_cfg);
zassert_true((r == 0), "Could not enable SPI ker_clk");
TC_PRINT("SPI1 ker_clk on\n");
/* Test ker_clk source */
spi1_dt_ker_clk_src = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(spi1), kernel, bus);
spi1_actual_clk_src = __HAL_RCC_GET_SPI1_SOURCE();
if (spi1_dt_ker_clk_src == STM32_SRC_PLL1_Q) {
zassert_equal(spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL,
"Expected SPI src: PLLQ (%d). Actual SPI src: %d",
spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL);
} else if (spi1_dt_ker_clk_src == STM32_SRC_PLL3_P) {
zassert_equal(spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL3,
"Expected SPI src: PLLQ (%d). Actual SPI src: %d",
spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL3);
} else {
zassert_true(1, "Unexpected ker_clk src(%d)", spi1_dt_ker_clk_src);
}
/* Test get_rate(ker_clk) */
r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &spi1_ker_clk_cfg,
&spi1_dt_clk_freq);
zassert_true((r == 0), "Could not get SPI clk freq");
spi1_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI1);
zassert_equal(spi1_dt_clk_freq, spi1_actual_clk_freq,
"Expected SPI clk: (%d). Actual SPI clk: %d",
spi1_dt_clk_freq, spi1_actual_clk_freq);
/* Test clock_off(reg_clk) */
r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
(clock_control_subsys_t) &spi1_reg_clk_cfg);
zassert_true((r == 0), "Could not disable SPI reg_clk");
zassert_true(!__HAL_RCC_SPI1_IS_CLK_ENABLED(), "SPI1 reg_clk should be off");
TC_PRINT("SPI1 reg_clk off\n");
/* Test clock_off(ker_clk) */
/* Not supported today */
}
void test_main(void)
{
ztest_test_suite(test_stm32h7_devices_clocks,
ztest_unit_test(test_sysclk_freq),
ztest_unit_test(test_spi_clk_config)
);
ztest_run_test_suite(test_stm32h7_devices_clocks);
}

10
tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/testcase.yaml Normal file
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common:
timeout: 5
platform_allow: nucleo_h723zg
tests:
drivers.stm32_clock_configuration.h7_dev.spi1_pllq_1_d1ppre_1:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pllq_1_d1ppre_1.overlay"
drivers.stm32_clock_configuration.h7_dev.spi1_pllq_2_d1ppre_4:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pllq_2_d1ppre_4.overlay"
drivers.stm32_clock_configuration.h7_dev.spi1_pll3p_1_d1ppre_4:
extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pll3p_1_d1ppre_4.overlay"