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tests/drivers/clock_control: stm32: Add test suite for H7 series

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Add clock_control test suite for H7 boards

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2021-12-17 11:32:09 +01:00 • committed by Carles Cufí
commit b5b32b9b3e
12 changed files with 404 additions and 0 deletions
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9
tests/drivers/clock_control/stm32_clock_configuration/stm32h7/CMakeLists.txt Normal file
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# SPDX-License-Identifier: Apache-2.0
cmake_minimum_required(VERSION 3.20.0)
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(stm32_clock_configuration_h7)
FILE(GLOB app_sources src/*.c)
target_sources(app PRIVATE ${app_sources})

64
tests/drivers/clock_control/stm32_clock_configuration/stm32h7/boards/clear_clocks.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay clears clocks back to a state equivalent to what could
* be found in stm32h7.dtsi
*/
&clk_hse {
status = "disabled";
/delete-property/ hse-bypass;
/delete-property/ clock-frequency;
};
&clk_hsi {
status = "disabled";
/delete-property/ hsi-div;
};
&clk_csi {
status = "disabled";
};
&clk_lse {
status = "disabled";
};
&clk_lsi {
status = "disabled";
};
&pll {
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-p;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
status = "disabled";
};
&pll3 {
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-p;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
status = "disabled";
};
&rcc {
/delete-property/ clocks;
/delete-property/ clock-frequency;
/delete-property/ d1cpre;
/delete-property/ hpre;
/delete-property/ d1ppre;
/delete-property/ d2ppre1;
/delete-property/ d2ppre2;
/delete-property/ d3ppre;
};

25
tests/drivers/clock_control/stm32_clock_configuration/stm32h7/boards/csi_4.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_csi {
status = "okay"; /* CSI RC: 4MHz */
};
&rcc {
clocks = <&clk_csi>;
clock-frequency = <DT_FREQ_M(4)>;
d1cpre = <1>;
hpre = <1>;
d1ppre = <1>;
d2ppre1 = <1>;
d2ppre2 = <1>;
d3ppre = <1>;
};

27
tests/drivers/clock_control/stm32_clock_configuration/stm32h7/boards/hse_8.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&rcc {
clocks = <&clk_hse>;
clock-frequency = <DT_FREQ_M(8)>;
d1cpre = <1>;
hpre = <1>;
d1ppre = <1>;
d2ppre1 = <1>;
d2ppre2 = <1>;
d3ppre = <1>;
};

26
tests/drivers/clock_control/stm32_clock_configuration/stm32h7/boards/hsi_64.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
status = "okay";
};
&rcc {
clocks = <&clk_hsi>;
clock-frequency = <DT_FREQ_M(64)>;
d1cpre = <1>;
hpre = <1>;
d1ppre = <1>;
d2ppre1 = <1>;
d2ppre2 = <1>;
d3ppre = <1>;
};

35
tests/drivers/clock_control/stm32_clock_configuration/stm32h7/boards/pll_csi_96.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_csi {
status = "okay"; /* CSI RC: 4MHz */
};
&pll {
div-m = <1>;
mul-n = <48>;
div-p = <2>;
div-q = <4>;
div-r = <2>;
clocks = <&clk_csi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(96)>;
d1cpre = <1>;
hpre = <1>;
d1ppre = <1>;
d2ppre1 = <1>;
d2ppre2 = <1>;
d3ppre = <1>;
};

37
tests/drivers/clock_control/stm32_clock_configuration/stm32h7/boards/pll_hse_550.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
div-m = <4>;
mul-n = <275>;
div-p = <1>;
div-q = <4>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(550)>;
d1cpre = <1>;
hpre = <2>; /* HCLK: 275 MHz */
d1ppre = <2>; /* APB1: 137.5 MHz */
d2ppre1 = <2>; /* APB2: 137.5 MHz */
d2ppre2 = <2>; /* APB3: 137.5 MHz */
d3ppre = <2>; /* APB4: 137.5 MHz */
};

37
tests/drivers/clock_control/stm32_clock_configuration/stm32h7/boards/pll_hse_96.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <24>;
div-p = <2>;
div-q = <4>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(96)>;
d1cpre = <1>;
hpre = <1>;
d1ppre = <1>;
d2ppre1 = <1>;
d2ppre2 = <1>;
d3ppre = <1>;
};

36
tests/drivers/clock_control/stm32_clock_configuration/stm32h7/boards/pll_hsi_96.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
hsi-div = <8>; /* HSI RC: 64MHz, hsi_clk = 8MHz */
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <24>;
div-p = <2>;
div-q = <4>;
div-r = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(96)>;
d1cpre = <1>;
hpre = <1>;
d1ppre = <1>;
d2ppre1 = <1>;
d2ppre2 = <1>;
d3ppre = <1>;
};

1
tests/drivers/clock_control/stm32_clock_configuration/stm32h7/prj.conf Normal file
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CONFIG_ZTEST=y

88
tests/drivers/clock_control/stm32_clock_configuration/stm32h7/src/test_stm32_clock_configuration.c Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <ztest.h>
#include <soc.h>
#include <drivers/clock_control.h>
#include <drivers/clock_control/stm32_clock_control.h>
#include <logging/log.h>
LOG_MODULE_REGISTER(test);
static void test_sysclk_freq(void)
{
uint32_t soc_sys_clk_freq;
soc_sys_clk_freq = HAL_RCC_GetSysClockFreq();
zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq,
"Expected sysclockfreq: %d. Actual sysclockfreq: %d",
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq);
}
static void test_sysclk_src(void)
{
int sys_clk_src = __HAL_RCC_GET_SYSCLK_SOURCE();
#if STM32_SYSCLK_SRC_PLL
zassert_equal(RCC_SYSCLKSOURCE_STATUS_PLLCLK, sys_clk_src,
"Expected sysclk src: PLL. Actual sysclk src: %d",
sys_clk_src);
#elif STM32_SYSCLK_SRC_HSE
zassert_equal(RCC_SYSCLKSOURCE_STATUS_HSE, sys_clk_src,
"Expected sysclk src: HSE. Actual sysclk src: %d",
sys_clk_src);
#elif STM32_SYSCLK_SRC_HSI
zassert_equal(RCC_SYSCLKSOURCE_STATUS_HSI, sys_clk_src,
"Expected sysclk src: HSI. Actual sysclk src: %d",
sys_clk_src);
#elif STM32_SYSCLK_SRC_CSI
zassert_equal(RCC_SYSCLKSOURCE_STATUS_CSI, sys_clk_src,
"Expected sysclk src: CSI. Actual sysclk src: %d",
sys_clk_src);
#else
/* Case not expected */
zassert_true((STM32_SYSCLK_SRC_PLL ||
STM32_SYSCLK_SRC_HSE ||
STM32_SYSCLK_SRC_HSI ||
STM32_SYSCLK_SRC_CSI),
"Not expected. sys_clk_src: %d\n", sys_clk_src);
#endif
}
static void test_pll_src(void)
{
uint32_t pll_src = __HAL_RCC_GET_PLL_OSCSOURCE();
#if STM32_PLL_SRC_HSE
zassert_equal(RCC_PLLSOURCE_HSE, pll_src,
"Expected PLL src: HSE (%d). Actual PLL src: %d",
RCC_PLLSOURCE_HSE, pll_src);
#elif STM32_PLL_SRC_HSI
zassert_equal(RCC_PLLSOURCE_HSI, pll_src,
"Expected PLL src: HSI (%d). Actual PLL src: %d",
RCC_PLLSOURCE_HSI, pll_src);
#elif STM32_PLL_SRC_CSI
zassert_equal(RCC_PLLSOURCE_CSI, pll_src,
"Expected PLL src: MSI (%d). Actual PLL src: %d",
RCC_PLLSOURCE_CSI, pll_src);
#else
zassert_equal(RCC_PLLSOURCE_NONE, pll_src,
"Expected PLL src: none (%d). Actual PLL src: %d",
RCC_PLLSOURCE_NONE, pll_src);
#endif
}
void test_main(void)
{
ztest_test_suite(test_stm32_syclck_config,
ztest_unit_test(test_sysclk_freq),
ztest_unit_test(test_sysclk_src),
ztest_unit_test(test_pll_src)
);
ztest_run_test_suite(test_stm32_syclck_config);
}

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tests/drivers/clock_control/stm32_clock_configuration/stm32h7/testcase.yaml Normal file
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common:
timeout: 5
platform_allow: nucleo_h723zg
tests:
drivers.stm32_clock_configuration.h7.sysclksrc_pll_hse_96:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_96.overlay"
drivers.stm32_clock_configuration.h7.sysclksrc_pll_hsi_96:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_96.overlay"
drivers.stm32_clock_configuration.h7.sysclksrc_hsi_64:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_64.overlay"
drivers.stm32_clock_configuration.h7.sysclksrc_csi_4:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/csi_4.overlay"
drivers.stm32_clock_configuration.h7.sysclksrc_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_8.overlay"
drivers.stm32_clock_configuration.h7.sysclksrc_pll_csi_96:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_csi_96.overlay"
drivers.stm32_clock_configuration.h7.sysclksrc_pll_hse_550:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_550.overlay"
platform_allow: nucleo_h723zg stm32h735g_disco