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tests/drivers/clock_control: stm32u5: Use a clear_clocks overlay

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Instead of relying on existing board clock configuration,
use a clear_clocks.overlay file to first reset the clock
configuration to the default .dtsi state, then apply a
new configuration.
This method should be more robust when trying to use on more
boards and has the benefit to provide correct configuration
examples.

This relies on the fact that overlays are applied in the order
they are provided in DTC_OVERLAY_FILE CMake variable.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2021-12-16 17:15:38 +01:00 • committed by Carles Cufí
commit 228a96e41e
14 changed files with 258 additions and 226 deletions
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39
tests/drivers/clock_control/stm32_clock_configuration/stm32u5/boards/b_u585i_iot02a_msis_24.overlay
View file

@ -1,39 +0,0 @@
/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay relies on initial board configuration.
* For clarity, nodes are over written instead of deleted.
* Any change to board configuration has impact on this file.
*/
&clk_lse {
status = "okay";
};
&clk_msis {
status = "okay";
msi-range = <1>; /* Range 1: 24MHz */
msi-pll-mode;
};
&pll1 { /* PLL disabled */
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
status = "disabled";
};
&rcc {
clocks = <&clk_msis>; /* clck src MSIS */
clock-frequency = <DT_FREQ_M(24)>; /* clck freq 24MHz */
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

39
tests/drivers/clock_control/stm32_clock_configuration/stm32u5/boards/b_u585i_iot02a_msis_48.overlay
View file

@ -1,39 +0,0 @@
/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay relies on initial board configuration.
* For clarity, nodes are over written instead of deleted.
* Any change to board configuration has impact on this file.
*/
&clk_lse {
status = "okay";
};
&clk_msis {
status = "okay";
msi-range = <0>; /* Range 0: 48MHz */
msi-pll-mode;
};
&pll1 { /* PLL disabled */
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
status = "disabled";
};
&rcc {
clocks = <&clk_msis>; /* clck src MSIS */
clock-frequency = <DT_FREQ_M(48)>; /* clck freq 48MHz */
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

43
tests/drivers/clock_control/stm32_clock_configuration/stm32u5/boards/b_u585i_iot02a_pll_hsi_160.overlay
View file

@ -1,43 +0,0 @@
/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay relies on initial board configuration.
* For clarity, nodes are over written instead of deleted.
* Any change to board configuration has impact on this file.
*/
&clk_lse {
status = "disabled"; /* LSE disabled */
};
&clk_msis { /* MSI disabled */
status = "disabled";
/delete-property/ msi-range;
/delete-property/ msi-pll-mode;
};
&clk_hsi { /* HSI enabled */
status = "okay";
};
&pll1 {
div-m = <4>; /* Update PLL config */
mul-n = <40>;
div-q = <2>;
div-r = <1>;
clocks = <&clk_hsi>; /* PLL src HSI */
status = "okay";
};
&rcc {
clocks = <&pll1>;
clock-frequency = <DT_FREQ_M(160)>; /* clck freq 40MHz */
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

43
tests/drivers/clock_control/stm32_clock_configuration/stm32u5/boards/b_u585i_iot02a_pll_hsi_40.overlay
View file

@ -1,43 +0,0 @@
/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay relies on initial board configuration.
* For clarity, nodes are over written instead of deleted.
* Any change to board configuration has impact on this file.
*/
&clk_lse {
status = "disabled"; /* LSE disabled */
};
&clk_msis { /* MSI disabled */
status = "disabled";
/delete-property/ msi-range;
/delete-property/ msi-pll-mode;
};
&clk_hsi { /* HSI enabled */
status = "okay";
};
&pll1 {
div-m = <4>; /* Update PLL config */
mul-n = <10>;
div-q = <2>;
div-r = <1>;
clocks = <&clk_hsi>; /* PLL src HSI */
status = "okay";
};
&rcc {
clocks = <&pll1>;
clock-frequency = <DT_FREQ_M(40)>; /* clck freq 40MHz */
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

48
tests/drivers/clock_control/stm32_clock_configuration/stm32u5/boards/clear_clocks.overlay Normal file
View file

@ -0,0 +1,48 @@
/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay clears clocks back to a state equivalent to what could
* be found in stm32u5.dtsi
*/
&clk_hse {
status = "disabled";
/delete-property/ clock-frequency;
/delete-property/ hse-bypass;
};
&clk_hsi {
status = "disabled";
};
&clk_lse {
status = "disabled";
};
&clk_msis {
status = "disabled";
/delete-property/ msi-range;
/delete-property/ msi-pll-mode;
};
&pll1 {
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
status = "disabled";
};
&rcc {
/delete-property/ clocks;
/delete-property/ clock-frequency;
/delete-property/ ahb-prescaler;
/delete-property/ apb1-prescaler;
/delete-property/ apb2-prescaler;
/delete-property/ apb3-prescaler;
};

29
tests/drivers/clock_control/stm32_clock_configuration/stm32u5/boards/msis_24.overlay Normal file
View file

@ -0,0 +1,29 @@
/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_lse {
status = "okay";
};
&clk_msis {
status = "okay";
msi-range = <1>;
msi-pll-mode;
};
&rcc {
clocks = <&clk_msis>;
clock-frequency = <DT_FREQ_M(24)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

29
tests/drivers/clock_control/stm32_clock_configuration/stm32u5/boards/msis_48.overlay Normal file
View file

@ -0,0 +1,29 @@
/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_lse {
status = "okay";
};
&clk_msis {
status = "okay";
msi-range = <0>;
msi-pll-mode;
};
&rcc {
clocks = <&clk_msis>;
clock-frequency = <DT_FREQ_M(48)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

50
tests/drivers/clock_control/stm32_clock_configuration/stm32u5/boards/nucleo_u575zi_q_pll_hse_160.overlay
View file

@ -1,50 +0,0 @@
/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay relies on initial board configuration.
* For clarity, nodes are over written instead of deleted.
* Any change to board configuration has impact on this file.
*/
/*
* Warning: HSE is not implmeneed on the board, hence:
* This configuration is only available for build
*/
&clk_lse {
status = "disabled"; /* LSE disabled */
};
&clk_msis { /* MSI disabled */
status = "disabled";
/delete-property/ msi-range;
/delete-property/ msi-pll-mode;
};
&clk_hse { /* HSE enabled */
status = "okay";
clock-frequency = <DT_FREQ_M(16)>; /* HSE clk freq 16MHz */
hse-bypass;
};
&pll1 {
div-m = <4>; /* Update PLL config */
mul-n = <40>;
div-q = <2>;
div-r = <1>;
clocks = <&clk_hse>; /* PLL src HSE */
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(160)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

39
tests/drivers/clock_control/stm32_clock_configuration/stm32u5/boards/pll_hse_160.overlay Normal file
View file

@ -0,0 +1,39 @@
/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
/*
* Warning: HSE is not implmeneted on available boards, hence:
* This configuration is only available for build
*/
&clk_hse {
status = "okay";
clock-frequency = <DT_FREQ_M(16)>;
hse-bypass;
};
&pll1 {
div-m = <4>;
mul-n = <40>;
div-q = <2>;
div-r = <1>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(160)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

32
tests/drivers/clock_control/stm32_clock_configuration/stm32u5/boards/pll_hsi_160.overlay Normal file
View file

@ -0,0 +1,32 @@
/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
status = "okay";
};
&pll1 {
div-m = <4>;
mul-n = <40>;
div-q = <2>;
div-r = <1>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll1>;
clock-frequency = <DT_FREQ_M(160)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

32
tests/drivers/clock_control/stm32_clock_configuration/stm32u5/boards/pll_hsi_40.overlay Normal file
View file

@ -0,0 +1,32 @@
/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
status = "okay";
};
&pll1 {
div-m = <4>;
mul-n = <10>;
div-q = <2>;
div-r = <1>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll1>;
clock-frequency = <DT_FREQ_M(40)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

9
tests/drivers/clock_control/stm32_clock_configuration/stm32u5/boards/b_u585i_iot02a_pll_msi_80.overlay → tests/drivers/clock_control/stm32_clock_configuration/stm32u5/boards/pll_msi_80.overlay
View file

@ -5,9 +5,8 @@
*/
/*
* Warning: This overlay relies on initial board configuration.
* For clarity, nodes are over written instead of deleted.
* Any change to board configuration has impact on this file.
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_lse {
@ -21,7 +20,7 @@
};
&pll1 {
div-m = <2>; /* Update PLL config */
div-m = <2>;
mul-n = <40>;
div-q = <2>;
div-r = <1>;
@ -31,7 +30,7 @@
&rcc {
clocks = <&pll1>;
clock-frequency = <DT_FREQ_M(80)>; /* clck freq 80MHz */
clock-frequency = <DT_FREQ_M(80)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;

38
tests/drivers/clock_control/stm32_clock_configuration/stm32u5/boards/pll_msis_160.overlay Normal file
View file

@ -0,0 +1,38 @@
/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_lse {
status = "okay";
};
&clk_msis {
status = "okay";
msi-range = <4>;
msi-pll-mode;
};
&pll1 {
div-m = <1>;
mul-n = <80>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_msis>;
status = "okay";
};
&rcc {
clocks = <&pll1>;
clock-frequency = <DT_FREQ_M(160)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

14
tests/drivers/clock_control/stm32_clock_configuration/stm32u5/testcase.yaml
View file

@ -3,27 +3,27 @@ tests:
timeout: 5
platform_allow: b_u585i_iot02a
drivers.stm32_clock_configuration.u5.sysclksrc_pll_msis_80:
extra_args: DTC_OVERLAY_FILE=boards/b_u585i_iot02a_pll_msi_80.overlay
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msi_80.overlay"
timeout: 5
platform_allow: b_u585i_iot02a
drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_160:
extra_args: DTC_OVERLAY_FILE=boards/b_u585i_iot02a_pll_hsi_160.overlay
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_160.overlay"
platform_allow: b_u585i_iot02a
timeout: 5
drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_40:
extra_args: DTC_OVERLAY_FILE=boards/b_u585i_iot02a_pll_hsi_40.overlay
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_40.overlay"
platform_allow: b_u585i_iot02a
timeout: 5
drivers.stm32_clock_configuration.u5.sysclksrc_msis_48:
extra_args: DTC_OVERLAY_FILE=boards/b_u585i_iot02a_msis_48.overlay
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/msis_48.overlay"
platform_allow: b_u585i_iot02a
timeout: 5
drivers.stm32_clock_configuration.u5.sysclksrc_msis_24:
extra_args: DTC_OVERLAY_FILE=boards/b_u585i_iot02a_msis_24.overlay
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/msis_24.overlay"
platform_allow: b_u585i_iot02a
timeout: 5
drivers.stm32_clock_configuration.u5.sysclksrc_pll_hse_160:
extra_args: DTC_OVERLAY_FILE=boards/nucleo_u575zi_q_pll_hse_160.overlay
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_160.overlay"
timeout: 5
platform_allow: nucleo_u575zi_q
build_only: true # Build only as HSE not implemened on the board
build_only: true # Build only as HSE not implemened on available boards