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tests/drivers/clock_control: stm32u5: Fix pll_msis_80 test config

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PLL input should be between 4 and 16MHz, so when MSI is set to 4MHz
fix PLLM can't be higher than 1.
Fix PLL1-NQR in consequence.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-03-04 16:44:36 +01:00 • committed by Carles Cufí
commit bc2a0b65a6
2 changed files with 6 additions and 6 deletions
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8
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_ahb_2_80.overlay → tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/pll_msis_ahb_2_40.overlay
View file

@ -21,9 +21,9 @@
&pll1 {
div-m = <1>;
mul-n = <40>;
div-q = <1>;
div-r = <1>;
mul-n = <80>;
div-q = <4>;
div-r = <4>;
clocks = <&clk_msis>;
status = "okay";
};
@ -31,7 +31,7 @@
&rcc {
clocks = <&pll1>;
ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
clock-frequency = <DT_FREQ_M(80)>;
clock-frequency = <DT_FREQ_M(40)>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;

4
tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/testcase.yaml
View file

@ -4,8 +4,8 @@ common:
tests:
drivers.stm32_clock_configuration.u5.sysclksrc_pll_msis_160:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_160.overlay"
drivers.stm32_clock_configuration.u5.pll_msis_hab_2_80:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_ahb_2_80.overlay"
drivers.stm32_clock_configuration.u5.pll_msis_hab_2_40:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_msis_ahb_2_40.overlay"
drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_160:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_160.overlay"
drivers.stm32_clock_configuration.u5.sysclksrc_pll_hsi_40: