Adds dts yaml bindings for the fxos8700 sensor to allow the sensor
driver name, i2c driver name, and i2c address to be extracted from dts
instead of kconfig.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Current buffers might be configured to skip data, thus only len will be
set, buf will be NULL. Buffer should be used if only len is > 0 and
buffer is valid as well.
tx/rx are "on" if len is > 0
tx/rx buf should be touched if only len is > 0 _and_ buf != NULL.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Move to new Kconfig pattern in which we use an if !HAS_DTS_I2C_DEVICE
block for the Kconfig symbols that can now come from DT generation.
This pattern is useful to allow us to define default values for the
generated symbols for build-all testing.
Fixes: #5877
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert NXP k6x and kw2xd flash driver to use device tree to get the
flash controller name from device tree. We introduce yaml bindings for
the "nxp,kinetis-ftfe" and "nxp,kinetis-ftfl" devices.
Fixes: #5788
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Transfer is an important concept of USB specification.
During a transfer, several packets can be transmitted.
Today the usb API only provides ep_read and ep_write
functions but the transfer concept is missing.
This is typically ok for basic drivers which don't have
to take care of how data is transfered/splitted.
However there are some drivers like CDC EEM, in which
transfer concept is important for packet management.
Moreover, current ep-write and ep_read method have a
different implementation in usb_dc_dw and usb_dc_stm32
device drivers. For example usb_dc_dw supports only
1-data-packet transfers due to its implementation.
This can increase latency and reduce performance.
I think this is something we need to fix/improve by
implementing better transfer management.
This patch introduces usb_dc_ ep_transfer method which
can be used to configure IN/OUT transfers. This allows
to configure and request different transfer sizes and
should prevent usage of the current stm32 temporary
buffer.
This method has asynchronous and synchronous mode.
Synchronous mode waits for transfer completion before
returning. Asynchronouse mode (irq safe) configures
the transfer and returns immediately, the provided
callback will be then called on transfer completion.
This also update ep_write and ep_read stm32 implementation
to use this new method but keep their behavior unchanged
for legacy reasons.
Note that for now this method is local to stm32 device
driver, however the goal would be to expose this function
as a new USB device driver API method so that class
drivers use it. This will request same implementation in
the usb_dc_dw_driver.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
usb mass example need usb_dc_ep_read_wait/continue API.
test usb mass storage with RAM DISK on stm32f4 series.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
Move to use an if HAS_DTS_I2C_DEVICE instead of depends on so that the
Kconfig sybmols don't even show up if HAS_DTS_I2C_DEVICE is true.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert Atmel SAM0 flash driver to use device tree to get the flash
controller name and base address.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Adds pinmux defines to use I2C2 at PB10/PB11 for
stm32f0-based boards.
Needed for stm32f072b_disco board to use extension
connector
Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
We want to move to use a common FLASH_DEV_NAME across the various flash
drivers. So samples, tests, or other code can be a bit more generic. So
replace CONFIG_SOC_FLASH_NRF5_DEV_NAME with FLASH_DEV_NAME.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Remove SoCs part dependency of CLOCK_STM32_PLL_PREDIV1 config since
it will only be used on parts having an HSE oscillator, ignored
otherwise.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The shared irq support doesn't really require its own dir, lets merge it
into drivers/interrupt_controller.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
So far, DT did not support the flash driver name.
Any flash-controller should have the appropriate
flash driver that should be identified by its name.
This path adds generic support for extract the description
from the flash-controller node,
adds implementation of this property for all nrf5x targets.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
The generic library provided by ST in ext/hal/st/lib/sensor/vl53l0x
needs to be adapted to the platform. In this case, the main
modification is the way to use I2C. This is now using the Zephyr
I2C API.
Signed-off-by: Vincent Veron <vincent.veron@st.com>
Add driver for ST vl53l0x time of flight sensor.
This driver can be used in 2 modes :
* proximity sensor :
configure VL53L0X_PROXIMITY_THRESHOLD
will return 1 if target is between sensor and threshold,
else, 0
* distance sensor :
will return the distance in millimeters from sensor to target
This driver use the official STMicroelectronics library for vl53l0x.
(in ext/hal/st/lib/sensor/vl53l0x)
Signed-off-by: Vincent Veron <vincent.veron@st.com>
Add gpio mcux driver which can be used for lpcxpresso54114 and other lpc
socs. In this driver, CMSIS register access is made for GPIO.
Option for access by GPIO Pin is provided as of now.
Signed-off-by: Shiksha Patel <shiksha.patel@nxp.com>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add usart-yaml in dts.
Build fsl_lpc_usart and fsl_lpc_flexcomm in
ext/hal/nxp/mcux/drivers/Makefile.
Only polling mode is implemented in usart now. Interrupt can be added in
future.
Signed-off-by: Shiksha Patel <shiksha.patel@nxp.com>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a new pinmux driver for lpcxpresso54114 based on mcux.
Signed-off-by: Shiksha Patel <shiksha.patel@nxp.com>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Use "select USE_STM32_LL_SPI" to select the needed STM32 LL files,
instead of editing ext/hal/st/stm32cube/CMakeLists.txt
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Use "select USE_STM32_LL_USB/USE_STM32_HAL_PCD/USE_STM32_HAL_PCD_EX"
to select the needed STM32 HAL files, instead of editing
ext/hal/st/stm32cube/CMakeLists.txt
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Use "select USE_STM32_LL_RNG" to select the needed STM32 LL files,
instead of editing ext/hal/st/stm32cube/CMakeLists.txt
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Use "select USE_STM32_HAL_TIM" to select the needed STM32 HAL files,
instead of editing ext/hal/st/stm32cube/CMakeLists.txt
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Use "select USE_STM32_LL_I2C" to select the needed STM32 LL files,
instead of editing ext/hal/st/stm32cube/CMakeLists.txt
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Use "select USE_STM32_HAL_ETH" to select the needed STM32 HAL files,
instead of editing ext/hal/st/stm32cube/CMakeLists.txt
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Use "select USE_STM32_LL_UTILS" to select the needed STM32 LL files,
instead of editing ext/hal/st/stm32cube/CMakeLists.txt
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
The CMakeLists lost the config for uart_mcux_lpsci.c, which is the
console driver for board frdm_kl25z. So just add "uart_mcux_lpsci.c"
into drivers/serial/CMakeLists.txt to make it work.
Signed-off-by: Jason Wang <jason.yanping.wang@hotmail.com>
In flash driver init, write_block_size could be initialized
with FLASH_WRITE_BLOCK_SIZE which is generated from device
tree parsing (dts property: "write-block-size")
Fixes#5305
If not defined, generate a compilation error.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
CC1200 is a sub-ghz chip supporting 6 ISM & SRD bands: 169, 433, 470,
868, 915 and 920 MHz, with features dedicated to IEEE 802.15.4(g).
Current driver enables CC1200 against actual IEEE 802.15.4 Soft-MAC. 'g'
version support in the Soft-MAC will follow later.
The chip itself is closer to a bare metal radio modem than to a usual
15.4 chip: up to the user to provide the right RF settings for the
carrier band. Such settings can be generaten through TI's SmartRF tool.
Hopefully, for channel selection, this driver will be clever enough to
compute the proper register change without any special input from the
user. This will work for all the bands supported by the chip.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Wrong buffer assigned for receiving the last 2 bytes in multi
byte reception of STM32F4 i2c driver. Change the buffer to
correct one.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This reverts commit 2a7efb7419.
"choice" section in board Kconfig.defconfig introduces a dependency
from the sensor to the board. As a consequence a warning was generated
whenever the sensor was used on another board.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This reverts commit 2e20f49167.
"choice" section in board Kconfig.default introduces a dependency
from the sensor to the board. Then a warning was generated
whenever the sensor is used on another board
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The SAM0 series has up to 6 SPI ports. Add Kconfig options to match.
Similar to the 9033fb2f01, this patch
only defines the fields that are currently used and skips ones like
GPIO and IRQ priority that aren't.
Signed-off-by: Michael Hope <mlhx@google.com>
It appears the STM32F411XE doesn't support RNG so remove enabling it
from the SoC defconfig and flag an error if attempting to build the
driver on that SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
According to STM32F4 reference manual, software should wait for BTF=1
before reading N-2 data byte.
Reference:
"For N >2 -byte reception, from N-2 data reception" section, page
853 of STM32F4 Reference manual.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
The SAM0 has a 64 byte page (the programing unit) with 4 pages to a
row (the erase unit). This driver implements a read/modify/write to
emulate the byte level writes used by NFFS.
Signed-off-by: Michael Hope <mlhx@google.com>
In STM32 family, RNG IP is available only on F4 and L4 series.
Besides STM32F401 does not support is neither.
Get entropy driver available on STM32 devices supporting it and
generate a compilation issue on STM32 devices that do not own
the RNG IP.
Solves #5448
Signed-Off-By: Erwan Gouriou <erwan.gouriou@linaro.org>
On STM32L4 SoCs RNG is clocked by 48MHz domain.
Hence, besides clock activation, it requires 48M
domain to be enabled.
Tested on:
*nucleo_l476rg
*stm32l476g_disco
*disco_l475_iot1
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
SPI_MODE_GET() returns a bitfield. It is thus wrong to test if a bit is
set using the equality operator. The bit-wise AND operator must be used
instead.
This can be tested by setting the SPI in mode 3 (CPOL + CPHA). Currently
both tests will fail and the result is a SPI configured in mode 0. This
was confirmed using an oscilloscope. Applying the patch fixes the
polarity.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
We can have a spurious error while performing a transfer using IRQ. This
happens when the last message of the transfer is a read with a STOP
condition. We must disable the RX interrupt while waiting for the STOP
interrupt, otherwise we will get a spurious RX interrupt which will lead
to an error.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
STM32 UART driver uses a macro for clock initialization, that
is difficult to read and incompatible with needed changes to
fix STM32F0 series UART problems.
This change switches to using the full clock bus names in UART
init functions removing the macro-magic and increasing
readability.
Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
The combination of
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL and
CONFIG_CLOCK_STM32_PLL_SRC_HSI
on SOCs with PREDIV1 support made use of the LL define
LL_RCC_PLLSOURCE_HSI_DIV_2, which is not defined for SOCs with
PREDIV1 support.
This exchanges LL_RCC_PLLSOURCE_HSI_DIV_2 with LL_RCC_PLLSOURCE_HSI
which is the appropiate source according to stm32f0xx_ll_rcc.h
line 473 and stm32f3xx_ll_rcc.h line 795.
Tested by compiling hello world for nucleo_f091rc board with HSI as
PLLSOURCE.
Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
Instead of accessing the environment variable ZEPHYR_BASE every time we
require accessing the source code root, use an intermediate variable
that has OS path separators correctly set to '/' to avoid issues on
Windows.
Note: This removes the ZEPHYR_SOURCE_DIR CMake variable. External
applications using that will need to change to use the new ZEPHYR_BASE
variable.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Old reference on driver's specific raw mode was still lurking around.
Removing those.
Fixes#5270
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
A very old reference to former net stack was still lurking around.
Removing it.
Taking the opportunity to clear up dependencies.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Amend stm32 ethernet driver with small changes:
*Provide HAL_ETH_Init return value in error message,
return on error and move it before thread creation
*Provide computed MAC address in debug message
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This was validated on the cc3220sf_launchxl board
using the Zephyr thermometer sample program
adapted to call the i2c driver directly, and fetching
samples from the on-board TMP006 temperature sensor.
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
This patch adds the driver for Panasonic AMG88xx
infrared array sensor.
The driver was developed within the framework of a student
internship in the development department. The task of the
student was to implement the trigger part of the driver,
transfer and visualization of the measured data.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
Of these, only struct net_ipv6_nbr_data::send_ns is a descriptive
change:
send_ns is used for timing Neighbor Solicitations in general, not
just for DAD.
The rest are typo/grammar fixes.
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
The PIO cores on Altera Nios-II processors can be used
for GPIOs and each PIO core can be configured as Input only,
Output only or as Bidirectional port from the Qsys tool.
The present Nios-II softcpu image on the Zephyr only has the
support for Output only port and the PIOs[0:3] are wired to
LED[0:3] on the Altera MAX10 board.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
In ARC's SecureShield, a new secure mode (currently only em) is added.
The secure/normal mode is orthogonal to kernel/user mode. The
differences between secure mode and normal mode are following:
* different irq stack frame. so need to change the definition of
_irq_stack_frame, assembly code.
* new aux regs, e.g, secure status(SEC_STAT), secure vector base
(VECT_BASE_S)
* interrupts and exceptions, secure mode has its own vector base;
interrupt can be configured as secure or normal through the
interrupt priority aux reg.
* secure timers. Two secure timers (secure timer 0 and timer 1) are
added.Here, for simplicity and backwards compatibility original
internal timers (timer 0 and timer1) are used as sys clock of zephyr
* on reset, the processor is in secure mode and secure vector base is
used.
Note: the mix of secure and normal mode is not supported, i.e. it's
assumed that the processor is always in secure mode.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Some drivers doesn't implement flash API page layout extension
which is causing the application crash once the API was calling.
This patch introduce system termination for this in those drivers
which doesn't implement extension. This will help to discover this
problem early.
It is not done by preprocessor check because it is possible to have
enabled a driver which support and a driver which doesn't support
this API simultaneously.
Now FLASH_PAGE_LAYOUT configuration option is accessible only in case
that at last one driver which implements mentioned API is enabled.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
On stm32f3_disco pins PF0/PF1 are used for OSC_IN/OSC_OUT
signals. Use pins PA9/PA10 for I2C_2 port
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Add the STM32F0 Embedded Flash support in the flash_stm32 driver
interface.
The STM32F0 has a particularity or use the HSI as clock source
for the flash controller interface, so this clock must be
enabled directly in the case HSE or another clock is used by
the system clock.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
IPv6 mcast addr to MAC mcast conversion was factored out to
subsys/net/ip/l2/ethernet.c for reuse by other drivers.
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Now that proper solicited-node multicast group joing is implemented,
promiscuous mode's purpose is reduced to just debugging needs.
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
This fixes a regression from
https://github.com/zephyrproject-rtos/zephyr/pull/5018
The ieee802154 driver wouldn't build because nrf drivers/ieee802154
depends on the nordic ext drivers to build.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Fix#5298
irq_is_pending function returned TXE/RXNE flag status
even if IRQ was masked, which led to enless loop
in uart_pipe when no TX was performed. Fix by reporting status only when
IRQ is unmasked.
Signed-Off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In uart_nrf5.c the IRQ masks for the TX READY and ERROR events are
incorrect. This pull request fixes the mask values so they are
according to the nRF51/nRF52832/nRF52840 product specification.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Added Inter-IC Sound driver (based on SSC module) for Atmel
SAM MCU family.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-2509
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Added DMA (XDMAC) driver for Atmel SAM MCU family. The driver provides
private DMA API to be used by the SAM family device drivers. Public
DMA API to be used by user space programs is currently missing.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-1609
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This patch makes minor improvements to the flash documentation:
* spi -> SPI
* Capitialise the first word in a sentance
* Adding the, and, all, etc where appropriate.
Signed-off-by: Michael Hope <mlhx@google.com>
Waiting for transfer complete and stop condition uses while loops
even when interrupt mode is enabled.
Implement use of TC, TCR and STOP interrupt for interrupt mode.
msg_done is not needed in interrupt mode anymore, so move it
to non-interrupt section
Tested with stm32f3_disco board.
Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
Disabling of Interrupts is duplicated. Move it to a position
that is common to messages that end with and without errors.
Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
As the nRF5x BLE controller uses TIMER1, TIMER2 and PPI
indices 0-13 (and 14-15, if PA/LNA feature is enabled),
the software based PWM driver needing 6 PPI channels has
to use PPI indices outside the BLE controller used range.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
- Renaming NET_L2_RAW_CHANNEL to NET_RAW_MODE
- Create a generic IEEE 802.15.4 raw mode for drivers
- Modify the IEEE 802.15.4 drivers so it passes the packet unmodified,
up to code using that mode to apply the necessary changes on the
received net_pkt according to their needs
- Modify wpanusb/wpan_serial relevantly
Fixes#5004
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Delete the native UART JTAG driver as we will be reusing
the Altera's HAL driver.
Add the shim driver support for Altera HAL's JTAG UART soft IP.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
Delete the native timer soft IP driver as we will be reusing
the Altera's HAL drivers for most of the soft IP's.
Add shim driver support for Altera timer system clock soft IP.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
Rename the Atmel SAM I2C driver based on TWIHS module to match the
convention:
<driver class>_<SoC family>_<hardware module used by the driver>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Various minor changes to the Atmel SAM (TWIHS) driver
- clean up variable names, comments
- refactor i2c_clk_set function
- do not save configuration in dev_data
- improve ISR NACK handling
- print "Device initialized" string
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Adds a new gpio driver for the NXP i.MX family of SoCs. Read, write,
configure, and callback API functions are all implemented.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Event ISR checks if the TX/RX interrupts is enabled instead
of the TXIS/RXNE interrupt status flags. Use the TXIS/RXNE
interrupt status flags to check which interrupt event
happened.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
STM32 I2C driver doesn't use the I2C API flags STOP/RESTART,
instead it uses its own RESTART flag. As a result, I2C API's
i2c_burst_write* funtions doesn't work. This patch makes
STM32 I2C driver to use I2C API flags.
Tested on: 96b_carbon, olimexino_stm32 (i2c_ll_stm32_v1)
Tested on: stm32f3_disco, disco_l475_iot1 (i2c_ll_stm32_v2)
Fixes: #4459
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Signed-off-by: Daniel Wagenknecht <wagenknecht@clage.de>
The interrupt priority on KW41Z is from 0..3. The value of 0x80 is
invalid, so lets set it to 0 for now as all the other interrupt
priorities default to 0 right now.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Added conditionally enabled event state tracing support.
Needed for enhanced debug visibility of tight timed events where
normal print debug messages affect the timing of things. This is a
simple buffer that allows post analysis via gdb of what sequencer
events occurred.
Signed-off-by: David Leach <david.leach@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
- Removed some debug output and changed the level of others to reduce
the amount of information logged. The reason is that some of this is
causing false positive distractions.
- Removed enabling of FILTER error IRQ events. It isn't needed and is
only informational.
- Changed frame control AR bit inspection to use native retrieval
routine.
- Addressed some coding style issues.
Signed-off-by: David Leach <david.leach@nxp.com>
Changed the logic to reset the sequencer when a RX filter
failure has been detected. This also disables the RX timer
until the next watermark detection.
Signed-off-by: David Leach <david.leach@nxp.com>
- Reworked the driver logic around TX/RX to correctly handle the
expectations of the underlying 802.15.4 hardware IP.
- Fixed a problem with TX always reporting an error to the stack
which resulted in constant retries.
- Fixed bug in RX to TX transition which would occasionally cause the
driver to error the TX.
- Changed RX logic to ensure that invalid RX frames were not passed up
the stack.
- Simplified hardware timer usage to only use TMR3.
- Added RX watermark and TMR3 support to fix a hardware problem where
the hw IP can get stuck on a receive in noisy environments.
- Modified samples/net/echo_client and echo_server kw41z project config
files to provide enanced debug visibility into stacks and threads.
Signed-off-by: David Leach <david.leach@nxp.com>
Instead of passing net_pkt as is to the receiving side of the
interface, clone the sent packet and drop the sent one.
This is needed mainly in TCP where passing the same packet from
sending to receiving side is causing havoc.
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
During large USB transfer it's pretty common to call ep_write whereas
the previous TX transfer is not achieved and so the TX FIFO space is
not available. Sleeping 20ms in this case introduce a relatively high
latency and reduce the throughput.
This can be observed when pinging the board with CDC-ECM net class.
ping reply is split into 2 USB TX transfer, the second one is only
triggered after 20ms, making ping latency > 20ms.
To fix this, just continuously read the FIFO availabilty and fire TX
as soon as possible.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
In the same way as dw driver, check that FIFO is empty before
writing any new data. This patch introduces a boolean semaphore
which is requested before any new TX transfer and released on
transfer completion.
This fixes usb-ecm support on 96b_carbon board.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Introducing CMake is an important step in a larger effort to make
Zephyr easy to use for application developers working on different
platforms with different development environment needs.
Simplified, this change retains Kconfig as-is, and replaces all
Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild
offers is replaced by a set of CMake extentions. These extentions have
either provided simple one-to-one translations of KBuild features or
introduced new concepts that replace KBuild concepts.
This is a breaking change for existing test infrastructure and build
scripts that are maintained out-of-tree. But for FW itself, no porting
should be necessary.
For users that just want to continue their work with minimal
disruption the following should suffice:
Install CMake 3.8.2+
Port any out-of-tree Makefiles to CMake.
Learn the absolute minimum about the new command line interface:
$ cd samples/hello_world
$ mkdir build && cd build
$ cmake -DBOARD=nrf52_pca10040 ..
$ cd build
$ make
PR: zephyrproject-rtos#4692
docs: http://docs.zephyrproject.org/getting_started/getting_started.html
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
Besides the fact that we did not have that for the current supported
boards, that makes sense for this new, virtualized mode, that is meant
to be run on top of full-fledged x86 64 CPUs.
By having xAPIC mode access only, Jailhouse has to intercept those MMIO
reads and writes, in order to examine what they do and arbitrate if it's
safe or not (e.g. not all values are accepted to ICR register). This
means that we can't run away from having a VM-exit event for each and
every access to APIC memory region and this impacts the latency the
guest OS observes over bare metal a lot.
When in x2APIC mode, Jailhouse does not require VM-exits for MSR
accesses other that writes to the ICR register, so the latency the guest
observes is reduced to almost zero.
Here are some outputs of the the command line
$ sudo ./tools/jailhouse cell stats tiny-demo
on a Jailhouse's root cell console, for one of the Zephyr demos using
LOAPIC timers, left for a couple of seconds:
Statistics for tiny-demo cell (x2APIC root, x2APIC inmate)
COUNTER SUM PER SEC
vmexits_total 7 0
vmexits_management 3 0
vmexits_cr 2 0
vmexits_cpuid 1 0
vmexits_msr 1 0
vmexits_exception 0 0
vmexits_hypercall 0 0
vmexits_mmio 0 0
vmexits_pio 0 0
vmexits_xapic 0 0
vmexits_xsetbv 0 0
Statistics for tiny-demo cell (xAPIC root, xAPIC inmate)
COUNTER SUM PER SEC
vmexits_total 4087 40
vmexits_xapic 4080 40
vmexits_management 3 0
vmexits_cr 2 0
vmexits_cpuid 1 0
vmexits_msr 1 0
vmexits_exception 0 0
vmexits_hypercall 0 0
vmexits_mmio 0 0
vmexits_pio 0 0
vmexits_xsetbv 0 0
Statistics for tiny-demo cell (xAPIC root, x2APIC inmate)
COUNTER SUM PER SEC
vmexits_total 4087 40
vmexits_msr 4080 40
vmexits_management 3 0
vmexits_cr 2 0
vmexits_cpuid 1 0
vmexits_exception 0 0
vmexits_hypercall 0 0
vmexits_mmio 0 0
vmexits_pio 0 0
vmexits_xapic 0 0
vmexits_xsetbv 0 0
See that under x2APIC mode on both Jailhouse/root-cell and guest, the
interruptions from the hypervisor are minimal. That is not the case when
Jailhouse is on xAPIC mode, though. Note also that, as a plus, x2APIC
accesses on the guest will map to xAPIC MMIO on the hypervisor just
fine.
Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
This is an introductory port for Zephyr to be run as a Jailhouse
hypervisor[1]'s "inmate cell", on x86 64-bit CPUs (running on 32-bit
mode). This was tested with their "tiny-demo" inmate demo cell
configuration, which takes one of the CPUs of the QEMU-VM root cell
config, along with some RAM and serial controller access (it will even
do nice things like reserving some L3 cache for it via Intel CAT) and
Zephyr samples:
- hello_world
- philosophers
- synchronization
The final binary receives an additional boot sequence preamble that
conforms to Jailhouse's expectations (starts at 0x0 in real mode). It
will put the processor in 32-bit protected mode and then proceed to
Zephyr's __start function.
Testing it is just a matter of:
$ mmake -C samples/<sample_dir> BOARD=x86_jailhouse JAILHOUSE_QEMU_IMG_FILE=<path_to_image.qcow2> run
$ sudo insmod <path to jailhouse.ko>
$ sudo jailhouse enable <path to configs/qemu-x86.cell>
$ sudo jailhouse cell create <path to configs/tiny-demo.cell>
$ sudo mount -t 9p -o trans/virtio host /mnt
$ sudo jailhouse cell load tiny-demo /mnt/zephyr.bin
$ sudo jailhouse cell start tiny-demo
$ sudo jailhouse cell destroy tiny-demo
$ sudo jailhouse disable
$ sudo rmmod jailhouse
For the hello_world demo case, one should then get QEMU's serial port
output similar to:
"""
Created cell "tiny-demo"
Page pool usage after cell creation: mem 275/1480, remap 65607/131072
Cell "tiny-demo" can be loaded
CPU 3 received SIPI, vector 100
Started cell "tiny-demo"
***** BOOTING ZEPHYR OS v1.9.0 - BUILD: Sep 12 2017 20:03:22 *****
Hello World! x86
"""
Note that the Jailhouse's root cell *has to be started in xAPIC
mode* (kernel command line argument 'nox2apic') in order for this to
work. x2APIC support and its reasoning will come on a separate commit.
As a reminder, the make run target introduced for x86_jailhouse board
involves a root cell image with Jailhouse in it, to be launched and then
partitioned (with >= 2 64-bit CPUs in it).
Inmate cell configs with no JAILHOUSE_CELL_PASSIVE_COMMREG flag
set (e.g. apic-demo one) would need extra code in Zephyr to deal with
cell shutdown command responses from the hypervisor.
You may want to fine tune CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for your
specific CPU—there is no detection from Zephyr with regard to that.
Other config differences from pristine QEMU defaults worth of mention
are:
- there is no HPET when running as Jailhouse guest. We use the LOAPIC
timer, instead
- there is no PIC_DISABLE, because there is no 8259A PIC when running
as a Jailhouse guest
- XIP makes no sense also when running as Jailhouse guest, and both
PHYS_RAM_ADDR/PHYS_LOAD_ADD are set to zero, what tiny-demo cell
config is set to
This opens up new possibilities for Zephyr, so that usages beyond just
MCUs come to the table. I see special demand coming from
functional-safety related use cases on industry, automotive, etc.
[1] https://github.com/siemens/jailhouse
Reference to Jailhouse's booting preamble code:
Origin: Jailhouse
License: BSD 2-Clause
URL: https://github.com/siemens/jailhouse
commit: 607251b44397666a3cbbf859d784dccf20aba016
Purpose: Dual-licensing of inmate lib code
Maintained-by: Zephyr
Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
This will accomodate newer access models later, with variations of those
functions' contents.
Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
nrf SOCs are capable of waking from Low power state or
Deep Sleep state using sense configuration.
So adding support for this in nrf GPIO driver.
Jira: ZEP-2623
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
The Makefile was using the obj-$FOO = form instead of the ob-$FOO +=
form, so if both slip and loopback are enabled then only loopback will
get built.
Signed-off-by: Michael Hope <mlhx@google.com>
In order to be able to default Kconfig "Trigger mode" choice
in a board Kconfig.defconfig, this commit provides it with a name.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Michael Hope
