This patch adds DTS support to the ARM CMSDK UART driver. The DTS
currently specifies the IRQ, IRQ PRIO, and base address of the port.
Change-Id: I8e5bc81c013958be4297d563495bf126b53a83a9
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds device tree support to the STM32 UART driver. The base
address, interrupt, and interrupt priority values can now come from DTS.
Change-Id: I3c383da8b200037601ecb2dc087f99ef103761bb
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch ifdef's out information that would be redefined by
information generated from DTS. This patch also fixes up the serial
drives to work properly with the DTS generated information.
Change-Id: I912ccf35be23c107705a4866e5a68b3b51154ffa
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds DTS support and related files for the NXP Kinetis
platform. The DTS files contain the base definitions for the hardware
nodes on Kinetis platforms. The YAML files provide the definitions of
the contents of the DTS nodes.
The Kconfig changes were put in place to allow for the conversion of
existing drivers. Once those drivers are modified, the Kconfig options
that are replaced by the DTS information will be removed.
Change-Id: If110fffa99c0b12471cf2df206da6687277e4756
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit removes unnecessary CONFIG_SYS_POWER_DEEP_SLEEP protection
in shim drivers as QMSI 1.4 has introduced empty context save/restore
functions that can be called in Quark D2000, therefore keeping common
code at the shim driver level for Quark SE and D2000.
Change-Id: Ia2a466327f999668c6511c0193014e9151bff6ae
Signed-off-by: Juan Solano <juanx.solano.menacho@intel.com>
Added basic USART driver for Atmel SAM MCU family. USART is a very
comprehensive module, currently only basic features sufficient to
support printf functionality are implemented by this driver.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-978
Change-Id: Ia9710e4069243fb6c30de45953dfc1fe1266b63a
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
Adds a shim layer around the mcux lpuart driver to adapt it to the Zephyr
serial interface.
NXP has multiple uart hardware blocks that implement different features
and have different register maps. The k64 has a uart block called
'uart', while the kw41 has a uart block called 'lpuart' (low power
uart). The MCUXpresso SDK provides separate drivers for each type of
uart block but with similar software interfaces. As a result, there are
also separate shim drivers in Zephyr. There is a 1:1:1 relationship
between hardware block, mcux driver, and mcux shim driver.
Because we now have two mcux shim drivers for the uart interface, a new
naming convention is created:
<interface>_mcux_<hw block>
Where <interface> is the name of the Zephyr interface, in this case
'uart'. This convention is not new.
<hw block> is the name of the NXP hardware block, in this case 'lpuart'.
This is the new part, and distinguishes different hardware blocks
for the same interface.
Change-Id: I3a80b9bffa116bbb2b02ee950d4bdd79a19a4edc
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The NXP copyright should not have 'Semiconductors, Inc' in it.
Change-Id: I6e290146d49bf22d1d40b7fa764bb53b6b122303
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Now that we have a more generic mcux serial driver, remove the uart_k20
driver.
Jira: ZEP-719
Change-Id: I51a3237454140feabbfe18ac2c8ee451e572c7be
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a shim layer around the mcux uart driver to adapt it to the Zephyr
serial interface. Unlike the existing (and confusingly-named) uart_k20
driver, this driver can be used for k64 and other Kinetis SoCs.
Implements polling and interrupt-driven serial interface functions that
are logically equivalent to the uart_k20 driver. Adds an extra instance,
irq_tx_empty(), and err_check() that aren't implemented in the uart_k20
driver.
Jira: ZEP-719
Change-Id: Iab99542e7ec921ef4f361437768113fee01e5fe8
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
riscv-qemu UART:
1) comprises only one register that is used to send or
receive characters in a polling fashion.
2) does not have a FIFO and is not interrupt-driven.
Change-Id: I9408f1776eba4cec4aa203a5da759ec04bcddf1f
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
UART 16750 is basically a UART 16550 with a 64-bytes FIFO.
The 64-bytes FIFO can be enabled via register FCR.
Account for it in the uart_ns16550 driver whenever the
CONFIG_UART_NS16750 variable is set.
Change-Id: I2342b28a41d03c96410bbfbe57e4b5a4e335731d
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
This patch adds the ARG_UNUSED macros to some function
arguments to avoid compiler warnings.
Change-Id: I628aea55d98cf8519c046ae5835e95cfa70a973f
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
To make way for the upcoming blinky and GPIO support for nRF5x-based
boards, this change addresses the hardcoded dependencies in Kconfig
default configurations of the different boards, moving the common option
defaults to the SoC default configuration itself.
Change-Id: I8db0750311ad5a12b76237b39438376f20f6f496
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The new Nordic MDK redefines certain UART signal names for backwards
compatibility with the new nRF52840 IC.
This patch addresses the potential name conflict between the redefined
signals and the existing variable names defined in the UART driver.
JIRA: ZEP-1418
Change-Id: I559d9335d2eeaa0a88d3f261b70508a1c98b989d
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This patch enables the clock control interface into the ARM LTD
CMSDK APB UART driver.
Jira: ZEP-1300
Change-Id: Ic0a214beb02d56ffb02ad4e6ca26b80805c0a4e6
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Deal with STM32L4X additions for clock and interrupt handling to the
uart driver.
Change-Id: I6e8dafb132dafea54b8f31a3a5cb6e35a207574d
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
There was a misalignment between Zephyr UART device numbering and
SoC UART IP. Device "UART_1" was mapped to IP USART_2, which could
be confusing for user.
This commit allows to align "UART_1" to IP USART_1.
Change is propagated to all STM32F103RB/STM32F401RE based boards and
respective pinmux drivers
Change-Id: Ia8099dfeec7b9c0c686c2a58ccb4dbb1a55b6537
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32Cube based implementation allows single driver file for
all stm32 based SoCs.
By maximizing code reuse, use of STM32Cube eases new SoCs
porting into Zephyr and provides better maintanability and
maturity.
Change-Id: Ief4b723add3dfc8b2a839683559c5a4c5d5eb837
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit replaces the nanokernel.h include by kernel.h.
Change-Id: Ib42fbf2d9f77a73c0831f569b3dbbfb342ea2e1d
Signed-off-by: Flavio Santes <flavio.santes@intel.com>
Add driver for CMSDK APB UART ports. The driver implements RX and TX
functionalities. Data transmission is implemented using polling and
interrupts. The driver default configuration for the port is to use
8bit data transmission, 1 stop bit, no parity control.
The driver exposes a public uart driver API and allows to register up
to five UART devices: from 'UART_0' to 'UART_4'. The driver performs
the required pinmux, the clock control configuration is left to the
platform.
The driver has been verified to work with the Hello World sample
application on a Beetle Board.
Jira: ZEP-1245
Change-Id: I5baf78b7659aae2a574d8e66205e6fd5eb579133
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
PRIMARY, SECONDARY, NANOKERNEL, MICROKERNEL init levels are now
deprecated.
New init levels introduced: PRE_KERNEL_1, PRE_KERNEL_2, POST_KERNEL
to replace them.
Most existing code has instances of PRIMARY replaced with PRE_KERNEL_1,
SECONDARY with POST_KERNEL as SECONDARY has had a longstanding bug
where the documentation specified SECONDARY ran before the kernel started
up, but actually ran afterwards.
Change-Id: I771bc634e9caf7f17dbf214a270bc9967eed7d32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The uart_k20 serial driver incorrectly assumed that all instances of the
UART peripheral are driven by the system clock, when actually some
instances are driven by the bus clock (which usually runs at half the
system clock). This caused incorrect baud rate calculations for UART
instances driven by the bus clock (UART2-4).
Change-Id: I38041781cdee146912bb5167e7c71d6416b966b5
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The pinmux configuration is done during board initialization.
This was validated using the following Zephyr apps:
- samples/hello_world
- samples/philosophers
- samples/drivers/uart
- samples/shell
UARTA0 is currently supported.
Change-Id: I85727c622d4d42183cc9f2f8b43d653e245dd17e
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Remove the Zephyr implementation and
update the uart_qmsi driver to use new QMSI PM APIs.
Jira: ZEP-998
Change-Id: I418e6384c16e374e9062820e12648a2d524a312d
Signed-off-by: JuanX Solano Menacho <juanx.solano.menacho@intel.com>
Use the macros provided by QMSI (or by ourselves, when QMSI doesn't
have them yet) to register interrupts independently of which core it's
building for.
Change-Id: I83fd7e42598b45aef8132316906a3bff291dfe92
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Update the QMSI drop we maintain in Zephyr, and fix the build where
needed:
- QM_SCSS_INT is renamed to QM_INTERRUPT_ROUTER;
- every member of QM_INTERRUPT_ROUTER was renamed as well;
- QM_IRQ_* renamed too, mostly added _INT at the end;
- some isr functions were renamed to keep their names consistent;
- build for x86 needs to define QM_LAKEMONT, as QM_SENSOR was for ARC.
Change-Id: I459029ca0d373f6c831e2bb8ebd52402a55994d1
Signed-off-by: Iván Briano <ivan.briano@intel.com>
Change the clock accessors to a tuple of bus ID of the subsystem and enable
bits for the device - it is clearer to read than the opaque pointers.
Change-Id: I9ae73c222c04adac4cf2bc06e97f4ec199bdac3c
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Ready To Send (RTS) hardware flow control signal in the nRF5
UART was being configured as an output with a pull-up on it.
This was seemingly causing certain issues with btattach on Linux
and it's not done anywhere else.
Change-Id: Id792d967b043ea7a796d6598500a733c092dbc2c
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The baudrate calculation present in set_baudrate() is
causing the UART to emit inital bytes incorrectly, for a
reason currently unknown, but directly related to the fact
that __aeabi_uldivmod is being invoked.
Since the nRF5x Product Specifications do not provide a
standard formula to calculate baudrates and instead list
a predefined set of divisor values, we opt here to use the
official values and remove the attempt at calculating them
manually.
Change-Id: Ic3ff42ea6d065e9a1d26a5350ce5bf5ad661160a
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The exact pin numbers for the nRF5 UART configuration is
board-specific, so the Kconfig default values should be in a
board-specific file.
Change-Id: Ibaacde292db191221e32b3626c68bf972dd26016
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Default IRQ priority changed to 1 to so it can also be compatible with
nRF51 (Cortex-M0 allows up to 4 priority levels but Zephyr needs the
first two for the OS).
Change-Id: Ie57a729f5d932f020a7d1d7e55cf3741f1ecfbab
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Integrating the IRQ definitions for both nRF51 and nRF52, and defining
the set of IRQ values that are common to both.
Also switch the controller, uart and clock drivers to use the common
header definitions.
Change-Id: Id6816d7a97720896cfe4df83656fb8b1f8fb01fa
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
The field is "NF: Noise detect flag". Given that every other field name is
faithful to the manual, do the same for NF.
Change-Id: I300663e6d5016bf28071d2a1926ec73682ae3d01
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Update the QMSI drop we maintain in Zephyr, and fix the build where
needed:
- QM_USB_BASE is renamed to QM_USB_0_BASE;
- parameter int_en from qm_uart cfg struct was removed;
- driver's folder now has a new structure, fix makefiles accordingly;
- QM_WDT_MODE and related renamed to QM_WDT_CR_RMOD;
- QM_SCSS_AON renamed to QM_AONC.
Change-Id: Iffe9c66b7a3f2fe64418326e20ff0894149b3044
Signed-off-by: Jesus Sanchez-Palencia <jesus.sanchez-palencia@intel.com>
The Atmel SAM3 serial driver poll in function checked
for new characters incorrectly.
Change-Id: I9024a991404bf949226634c9f6c6ea507577cff1
Signed-off-by: Justin Watson <jwatson5@gmail.com>
PCI enumeration modifies pci_dev and port at driver initialization,
these objects move from config_info to driver_data in preparation for
config_info becoming const.
This driver shares a unified uart configuration structure with other
uart device drivers. The structure uses 'union' and the preprocessor
to customize the structure to the drivers specific requirement. There
appears to be no compelling reason why all the uart drivers should
share the same (customized) config_info structure. In order to
re-organize the structure for this driver to get config_info const, an
ns16550 specific config structure is defined and the driver switched
over from the generic uart_config.
Change-Id: I31932d811f623a9370b69903114ae97b15d65886
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Make pointers to struct config_info const in prepration for a const
config_info.
Change-Id: I0257e242a2d3bc4e353a3477364a4d9a7fb72b82
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The drivers config structure initializer sets sys_clk_freq statically.
The runtime repeated setup of sys_clk_freq is superfluous, and
inconsitent with const driver config structures.
Change-Id: I115e2b70b193b567de83132f3984e48b2dded0a2
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Make pointers to struct config_info const in prepration for a const
config_info.
Change-Id: I8ecc10b50e23d2dbe987e3318bac09e235b1e1da
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@gmail.com>
Updated CONFIG_SOC_QUARK_SE_SS to CONFIG_SOC_QUARK_SE_C1000_SS
Change-Id: I7dc02d91a4d739f6cd3f84001d1dd29759317163
Signed-off-by: Javier B Perez <javier.b.perez.hernandez@intel.com>
Update the power sample and drivers with the new device driver power
management API using the existing logic
Jira: ZEP-954
Change-Id: Idd94232e458767635973e94e9fc673c01612c1e2
Signed-off-by: Amir Kaplan <amir.kaplan@intel.com>
The Sensor Subsystem has different IRQ numbers for the same device
across CPUs. QMSI declares these, but doesn't do anything to try to
map it automatically, so we have to do it in the driver.
Similarly the SCSS interrupt routing (the SoC-wide "APIC", which is
distinct from the per-CPU interrupt masking hardware) needs to know
which CPU we're trying to unmask an interrupt for.
Change-Id: I27e5ec44f324f869e16a92e7ef40a22a305d98a2
Jira: ZEP-546
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Completing the terminology change started with change 4008
by updating the Kconfig files processed to produce the
online documentation, plus header files processed by
doxygen. References to 'platform' are change to 'board'
Change-Id: Id0ed3dc1439a0ea0a4bd19d4904889cf79bec33e
Jira: ZEP-534
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
One remaining reference to uart_qmsi_pm_save_config
was missed by patch bc60506d3e.
This reference is removed.
This fixes the following error:
...
drivers/built-in.o: In function `uart_qmsi_line_ctrl_set':
/drivers/serial/uart_qmsi.c:439:
undefined reference to `uart_qmsi_pm_save_config'
collect2: error: ld returned 1 exit status
...
Change-Id: I1ceda0e152db5a1c7f70d67c04b931416687031a
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
In order to restore uart context after entering
SYS_PM_DEEP_SLEEP, suspend and resume functions
are called.
The following parameters are restored:
- All registers for the UART device.
- UART clocks.
The FIFO control register cannot be read back and is
not stored in the device configuration.
The default parameters are applied for them.
The suspend/resume functionality is implemented in
the QMSI shim layer as a fast and temporary solution,
it will be removed and migrated to QMSI later.
Change-Id: I4be9246f6aa5a6e0d91df54c1c69574060136607
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
CONFIG_UART_INTERRUPT_DRIVE should be CONFIG_UART_INTERRUPT_DRIVEN
CONFIG_UART_LINE_CTR should be CONFIG_UART_LINE_CTRL
Change-Id: I11fba5b387e3d36711cd3c813fc8a297ae23af05
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The macro defining the device_pm_ops structs is located inside an
ifdef for CONFIG_UART_QMSI_0, so when the UART_0 is disabled at build
time, but UART_1 is still used, it references a struct not defined.
Fix it by placing the DEFINE_DEVICE_PM_OPS line outside the ifdef block.
Change-Id: I7dafda162741201ee47b5b480c07ec8c1f373d64
Signed-off-by: Iván Briano <ivan.briano@intel.com>
This adds some basic suspend/resume support in the uart_qmsi
driver. This is part of a change to enable device suspend/resume
and deep sleep support in sample PM application.
Jira: ZEP-512
Change-Id: I38cfbfb352d0027b7beaadebedbc10002dade50a
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Use IOAPIC_EDGE instead of IOAPIC_LEVEL to fix missing interrupts.
During tests it was found that using IOAPIC_LEVEL interrupts for UART at
some points are lost.
Proposed by Calando, Antoine <antoine.calando@intel.com>
Change-Id: I18b20217c4d73fdeaa424bf59d00f6be1ec6ef1b
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Revert patch fixing Bluetooth application with Debug enabled crashing.
This reverts commit 029d3beb57.
Change-Id: I0004dae656ca5a0b44da9f12542088d47c38b837
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
QMSI uart driver has removed qm_uart_get_config API. Updated
the shim driver to use alternatives.
Change-Id: I3ccfd0dfec3711d250de7d1004275d9b02d7477a
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
Signed-off-by: Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
Global data and device setting can be messed up by concurrent
API calls. This change is to serialize the access.
Jira: ZEP-454
Change-Id: I520722aecab7db443d053fd45498a22e165889de
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
This currently only supports outgoing messages without interrupts.
Change-Id: I635562f47106eb6cdc7104a8160e431bebea25dc
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
In order to change the baudrate the DLAB bit of the LCR register has to
be set to 1 (This bit is used to enable reading and writing of the
divisor latch register). This bit must be cleared after the baudrate
setup in order to access other registers.
The set_baud_rate function correctly sets the DLAB bit of the LCR reg but
never clears it. Therefore the ns16550 doesn't properly work any more
after updating the initial baud rate.
In order to fix this issue the LCR reg has to be temporary saved
(because it contains other important settings). After switching to a new
baud rate the LCR reg value has to be restored.
Change-Id: Ied4db683cbf40ba3125e747552968ddf1a66e2be
Signed-off-by: Jeremie GARCIA <jeremie.garcia@intel.com>
Signed-off-by: Sebastien GRIFFOUL <sebastien.griffoul@intel.com>
Convert leading whitespace into tabs in Kconfig files. Also replaced
double spaces between config and <prompt>.
Change-Id: I341c718ecf4143529b477c239bbde88e18f37062
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
On current Curie-based boards UART 0 is wired to the nRF51 BLE
controller and requires HW flow control to be enabled in order to
function. This patch restores the same behavior that was present
before the "qmsi: uart: use built-in qmsi driver" patch.
Change-Id: If7ea347f5ab8b460f39123dcc0d75d711a5a1c2a
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use SOC_SERIES_* for naming SoCs with similar features and architectures
with the goal of code reuse. The Series in the config variable should avoid
name collisions and clearly denote the relationships within an SoC family.
Change-Id: I7a98542f96b5d5dc3acc23782c4d45f98cceb599
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Use CONFIG_SOC_FAMILY for the top level SoC family. A family
will have different SoCs or different SoC series with multiple
SoCs.
Adding the Family string to the config variable to avoid confusion
between actual SoCs and families and to prevent name collisions.
Change-Id: Ic99a2c1df7850dee3a45641027af82464dd6fadb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Note that the failure case can only be reached when PCI is enabled.
Otherwise, the if-block is always false, which reduces code size
for non-PCI platforms.
Change-Id: Ib98b78a75cc2a5f124e67f32f2bf82960a963aec
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The IRQ triggering condition should be specified by SoC as it is
a decision for hardware design. This should not be configurable
in kconfig.
The default is to be triggered on rising edge, just as the same
old kconfig did.
Change-Id: If59d88a30711eb8e03d9cc4f409055cefe1995c5
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Moves those kconfig options which should be declared in
SoC or board header files instead. These are the one
that are tied to SoC or board and there is no need
for them to be configurable in kconfig.
Change-Id: I243d634f1a4a11dc8dc3530d95f93371015492b7
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The UART port base address, IRQ line and clock frequency are static
per SoC, so there is no need to make them configurable in Kconfig.
Change-Id: Ia252958d205e0100d1b92e2a12d4c22411bc94b9
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The UART port base address, IRQ line and clock frequency are static
per SoC, so there is no need to make them configurable in Kconfig.
Change-Id: I79b142414143bc5ef585d3136a00375233de1723
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch fixes the QMSI UART shim driver so we are able to use it in
Quark D2000 based platforms. Differently from Quark SE, the peripheral
clock gate bit (CLK_PERIPH_CLK) is not enabled by default in Quark
D2000. We have to explicitly set this bit in order to properly initialize
the device.
Since this drivers is now properly working on Quark D2000, this patch
also sets the QMSI driver default options in arch/x86/soc/quark_d2000/
Kconfig.
Change-Id: I817b7703554be162ac628dcd8d3d07512b9eb3f5
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
The patch extends STM32 serial port driver with support for IRQ API of
the common UART port driver API.
Change-Id: If105e8528ea4ed4181cc4af0c97c24aa874e69e0
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
Add driver for U(S)ART ports on STM32 MCUs. The driver implements basic
RX/TX functionality. Data transmission is implemented using polling. The
driver configures the port to use 8bit data transmission, 1 stop bit, no
parity control.
The driver exposes a public uart driver API and registers a single UART
device 'UART_0'. The device binds to USART1 peripheral and performs
required pinmux and clock control configuration. The device can be
initialized at the PRIMARY level, with default device priority.
The driver has been verified to work with a sample Hello World
application on a STM32F103 series MCU.
Change-Id: Iae103fcd8d2fb0a6c173cf141a68e17791255aab
Origin: Original
Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
() Adds some comment to divide config options for easier
visual navigation.
() Put config under submenus to make all driver options
consistent with each other.
Change-Id: Ia219c5283e4fa394adf8b0ac03577a0fd033ec1c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch replaces all occurences of the macro DEV_NO_SUPPORT by
-ENODEV at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I03007527367b03e6fd72a85004b7d3b81046a6a6
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_INVALID_CONF by
-EINVAL at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: Idae0d5af8dd780416977c9261a5fb6188c3aab64
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_INVALID_OP by
-ENOTSUP at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/ when applicable.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I46aec3c65963018c479b01602e4a3eec8650eaff
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch replaces all occurences of the macro DEV_OK by the actual
value 0 at the driver level. So this patch touch the files under
drivers/, include/ and samples/drivers/.
This patch is part of the effort to transition from DEV_* codes to
errno.h codes.
Change-Id: I69980ecb9755f2fb026de5668ae9c21a4ae62d1e
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch extends the UART QMSI driver so it supports the IRQ APIs from
include/uart.h. The IRQ APIs are enabled by the 'CONFIG_UART_INTERRUPT_
DRIVEN' option.
Differently from others APIs such as I2C and SPI, the UART API is very
low level. For that reason, the IRQ facilities (e.g. irq based transfers)
from the QMSI driver are not useful to the shim driver at the moment. In
order to implement the IRQ APIs we rely on UART registers defined by QMSI.
QMSI UART header is missing some macro definitions from IRR register so
we define them in the shim driver.
Since the IRQ trigger condition is not configurable in the QMSI shim
driver, this patch also changes drivers/serial/Kconfig so the "UART
IRQ Trigger Condition" choice doesn't appear on the menu if the QMSI
driver is selected.
Change-Id: Idf9a0f6a47af2a550a31f474d721068dca989713
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch extends the UART QMSI driver so it supports line control and
driver command APIs.
The line control function supports the baud rate option only (LINE_CTRL_
BAUD_RATE) and, at the moment, the QMSI driver doesn't have any custom
command.
Change-Id: Icc10cb39b4077ed4ccfefb1f0feecec75b79d67c
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch extends the UART QMSI driver so it supports different baud
rate configurations. The baud rate is set per UART controller via
menuconfig. The default baud rate is 115200.
Change-Id: Iad736d72bd309b8a33ab5d538251fce374e89fd2
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This patch introduces the QMSI UART driver which is simply a shim driver
based on UART driver provided by QMSI BSP.
This initial version implements only the mandatory APIs 'poll_in',
'poll_out' and 'err_check' which are required by trivial sample apps and
by output functionality from the console driver. The remaining APIs will
be implemented by up coming patches. The driver supports only 115200 baud
rate at the moment.
In order to enable this driver, the following options should be set:
CONFIG_QMSI_DRIVERS=y
CONFIG_QMSI_INSTALL_PATH="/path/to/libqmsi/directory"
CONFIG_SERIAL=y
CONFIG_UART_QMSI=y
This driver has been tested with Quark SE Devboard so this patch also
adds its platform-specific default configuration options to 'arch/x86/
soc/quark_se/Kconfig'.
Change-Id: Ibde1825d4b0349a376a8e7d91cc9de306946b62f
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
The peripherals utilizing UART were required to register their own
ISR rountines. This means that all those peripherals drivers need
to know which IRQ line is attached to a UART controller, and all
the other config values required to register a ISR. This causes
scalibility issue as every board and peripherals have to define
those values.
Another reason for this patch is to support virtual serial ports.
Virtual serial ports do not have physical interrupt lines to
attach, and thus would not work.
This patch adds a simple callback mechanism, which calls a function
when UART interrupts are triggered. The low level plumbing still needs
to be done by the peripheral drivers, as these drivers may need to
access low level capability of UART to function correctly. This simply
moves the interrupt setup into the UART drivers themselves. By doing
this, the peripheral drivers do not need to know all the config values
to properly setup the interrupts and attaching the ISR. One drawback
is that this adds to the interrupt latency.
Note that this patch breaks backward compatibility in terms of
setting up interrupt for UART controller. How to use UART is still
the same.
This also addresses the following issues:
() UART driver for Atmel SAM3 currently does not support interrupts.
So remove the code from vector table. This will be updated when
there is interrupt support for the driver.
() Corrected some config options for Stellaris UART driver.
This was tested with samples/shell on Arduino 101, and on QEMU
(Cortex-M3 and x86).
Origin: original code
Change-Id: Ib4593d8ccd711f4e97d388c7293205d213be1aec
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Not all of the variables defined in the driver data structure are
required. So put some #ifdef around them.
Change-Id: I08a0c02d9e5c6885d9b4d6237446bdb9b98f3bfa
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Looking at all structs as to where we can pack them a little better, and
calling out the padding/stride at the end for future expansion.
Change-Id: I4a651092e950dd3d915af9fa0ee0d7d59803e58f
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is the last step before obsoleting DEVICE_DEFINE() and
DEVICE_INIT_CONFIG_DEFINE().
Change-Id: Ica4257662969048083ab9839872b4b437b8b351b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename it to DEVICE_DEFINE() so that it fits in the 'device' namespace.
Change-Id: I3af3a39cf9154359b31d22729d0db9f710cd202b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename it to DEVICE_INIT_CONFIG_DEFINE(), because (a) it was not fitting
in any namespace and (b) it is not used to declare, but rather define a
object.
Change-Id: I1da5822f06b85a9fb024b5b184afd0ccc01012ec
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Adds extern "C" { } blocks to header files so that they can be
safely used by C++ source files.
Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
This adds driver for the UART controller on Atmel SAM3X8E.
This UART controller only has two wires for RX and TX, and
does not have flow control (e.g. CTS, RTS) or FIFO.
Currently, the driver does not support any interrupt driven
operations.
Change-Id: I63720bccfb70a89888353b8ee3dfc4b80793dc01
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This API is not being used for anything, the interrupts for UART
drivers are all being configured statically. Saves code space as
gc-sections can't tell that these APIs are unused.
Some instances where IRQ/priority information was being saved in
data structures and never used fixed.
Change-Id: If56b4fdc251b80be9094ffcbac6f61e265ac2ffd
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This implements the newly introduced APIs to manipulate line controls
for UART.
This also implements the driver command API as setting baud rate
may require setting the DLF.
Change-Id: I80634aa3fbd4a3223c46edb61417123e36f439dd
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds 2 new APIs to the serial/uart drivers:
() One is to control the serial line, such as RTS and CTS.
() Another one is to allow driver to expose hardware specific functions
to apps. This is needed as some hardware may have extra registers to
set for baud rate.
To keep the code size small, these features are disabled by default.
Change-Id: I15c000ce68a0a490dcfd3493b2fe9bc51fa974fa
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves the baud rate and options fields out of the UART driver
config struct and into the driver data struct. This will allow
changing baud rate and options at runtime in the future.
Change-Id: I62ddea2f95e634f2d60eeb9537f960799fc9301f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The UART on Quark SE and D2000 supports fractional clock divider.
It is used to limit frequency error for supported baud rates.
Change-Id: I1f39a95db09f4a5a4116edc700a10e4b9ecfa2bd
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Rename class in pci_dev_info struct to allow to use C++ compilers.
Updated drivers to use new struct.
Change-Id: I17b94cb7bc094bccd615c8389a28589bfa90cab8
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Only the first port is currently enumerated on the PCI bus. As a result,
the second port configuration will be set based on the default options,
that may be invalid on some platforms.
Fix this by enumerating the second port as well.
Change-Id: I63733a1f13f7cb35cae1dba3b6192dcd61c9f644
Signed-off-by: Ido Yariv <idox.yariv@intel.com>
Signed-off-by: Ido Yariv <ido@wizery.com>
Change terminology and use SoC instead of platform. An SoC provides
features and default configurations available with an SoC. A board
implements the SoC and adds more features and IP block specific to the
board to extend the SoC functionality such as sensors and debugging
features.
Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The code to poke the system integration module to disable clock gating
for UARTs only works for UART0-3 since all the bits are in the same
register. However, clocks for UART4 and UART5 are controlled by
another register. This means that we have been writing to the wrong
bit for enabling UART4.
This patch fixes this issue, and moves the clock gating clock into
board initialization. The incorrect code has also been removed to
prevent accidental mis-use. The dev_data struct is no longer needed
for uart_k20, so that is removed as well.
Change-Id: I67845a417e43647bf0ffcbdbda34ce68fa887713
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Instead of having two config options to specify interrupt triggering
conditions, merge them into one option and clarify. This is now
similar to other drivers which have interrupt triggers.
Change-Id: I4e60c8c45a08d005dcc8256cb89e4c5be7c94307
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds CONFIG_UART_NSIM to enable the uart/nsim driver.
This fixes compilation issue where the base address parameter
is not defined due to CONFIG_NSIM=y but CONFIG_SERIAL=n.
Change-Id: I1dc1c15b22ad174d4db514d89551780f0dfcae66
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Since all the necessary bits utilizing UART by index have moved to
use device name instead, the uart_devs[] can finally be removed.
Change-Id: Idbae6b46c0af9eef6c22c59e121e9d6a6b52426a
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove unused code after refactoring all the serial/UART drivers.
() Since device initialization is done by the drivers themselves,
there is no need to have config_func(), port_init() and uart_init()
to perform configuration external to driver. So remove the related
bits.
() The IRQ priority is only being used when doing IRQ_CONNECT_STATIC().
So there is no need to send it over during uart_init().
Change-Id: I72eb3402036b53cbc01c1eb968de0ddfa0096ee2
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Since the initialization is now done within driver, there is
no need to expose the port_init() function externally anymore.
After the consumers of port_init() have been updated. It is time
to perform the final step.
Change-Id: Ibe22c6d1dc9525c845acc094fa2066c922439ec3
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Since the initialization is now done within driver, there is
no need to expose the port_init() function externally anymore.
After the consumers of port_init() have been updated. It is time
to perform the final step.
Change-Id: Iba7aeb056edd63ef3f9b47d3801a3e0eeb9b34d5
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Since the initialization is now done within driver, there is
no need to expose the port_init() function externally anymore.
After the consumers of port_init() have been updated. It is time
to perform the final step.
Change-Id: I4e0d0a6802ddda4a6671c6d246233eaa5074d4ff
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Rename nsim_uart.c to uart_nsim.c. This is to follow
the driver naming convention.
() Rename functions nsim_uart_*() to uart_nsim_*(),
following driver naming convention.
() UART ports initialization is moved into the driver itself.
All the init code in platform config files is removed.
() Adds (many) Kconfig options. These don't have to be defined
in each platform's board.h anymore.
Change-Id: If015f39a6f6b4fcc65625e6e5f973b4469202f54
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Renames stellarisUartDrv.c to uart_stellaris.c. This is to follow
the driver naming convention.
() Renames functions stellaris_uart_*() to uart_stellaris_*(),
following driver naming convention.
() Renames CONFIG_STELLARIS_UART* to CONFIG_UART_STELLARIS*
() UART ports initialization is moved into the driver itself.
All the init code in platform config files is removed.
() Adds (many) Kconfig options. These don't have to be defined
in each platform's board.h anymore.
Change-Id: I0eadc3878d69ff24d1637f8df5220fd2f161d24f
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Rename k20UartDrv.c to uart_k20.c. This is to follow the driver
naming convention.
() Move driver/serial/k20_uart.h to drivers/serial/uart_k20_priv.h
as this contains definitions private to the driver, and
should not be exposed in public include directory.
() Rename functions k20_uart_*() to uart_k20_*(), following
driver naming convention.
() Renames CONFIG_K20_UART_* to CONFIG_UART_K20_*
() UART ports initialization is moved into the driver itself.
All the init code in platform config files is removed.
() Adds (many) Kconfig options. These don't have to be defined
in each platform's board.h anymore.
Change-Id: If1be1fde083aba6ff68062db2059aef08617a286
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
() Renames ns16550.c to uart_ns16550.c. This is to follow
the driver naming convention.
() Renames functions ns16550_uart_*() to uart_ns16550_*(),
following driver naming convention.
() UART ports initialization is moved into the driver itself.
All the init code in platform config files is removed.
() Adds (many) Kconfig options. These don't have to be defined
in each platform's board.h anymore.
() Renames CONFIG_NS16550_* to CONFIG_UART_NS16550_*
() Disable NS16550 for ARC as no port is defined anyway.
Change-Id: I76bbe25b9bc75eb62df81e533f84f4f63a5257b7
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Due to a quirk of the k20 UART, when checking if either a Tx or Rx
irq is ready, one must first check whether the UART has enabled the
Tx and/or Rx interrupts. If this is not done, then all one is doing
is testing the UART to determine if it is ready to Tx and/or Rx.
Change-Id: I08a8280ed9fb0faef586f3c7d7befb3bfdec1e2d
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
