uart: stm32: add support for STM32F4
Change the clock accessors to a tuple of bus ID of the subsystem and enable bits for the device - it is clearer to read than the opaque pointers. Change-Id: I9ae73c222c04adac4cf2bc06e97f4ec199bdac3c Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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cc655ca377
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3 changed files with 43 additions and 3 deletions
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@ -24,4 +24,7 @@
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#define STM32F4_PINMUX_FUNC_PB6_USART1_TX STM32_PINMUX_FUNC_ALT_7
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#define STM32F4_PINMUX_FUNC_PB7_USART1_RX STM32_PINMUX_FUNC_ALT_7
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#define STM32F4_PINMUX_FUNC_PA2_USART2_TX STM32_PINMUX_FUNC_ALT_7
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#define STM32F4_PINMUX_FUNC_PA3_USART2_RX STM32_PINMUX_FUNC_ALT_7
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#endif /* _STM32F4_PINMUX_H_ */
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@ -62,7 +62,12 @@ static void set_baud_rate(struct device *dev, uint32_t rate)
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* peripheral. Ask clock_control for the current clock rate of
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* our peripheral.
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*/
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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clock_control_get_rate(data->clock, cfg->clock_subsys, &clock);
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#elif CONFIG_SOC_SERIES_STM32F4X
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clock_control_get_rate(data->clock,
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(clock_control_subsys_t *)&cfg->pclken, &clock);
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#endif
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/* baud rate calculation:
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*
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@ -286,7 +291,11 @@ static int uart_stm32_init(struct device *dev)
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__uart_stm32_get_clock(dev);
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/* enable clock */
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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clock_control_on(data->clock, cfg->clock_subsys);
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#elif CONFIG_SOC_SERIES_STM32F4X
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clock_control_on(data->clock, (clock_control_subsys_t *)&cfg->pclken);
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#endif
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/* FIXME: hardcoded, clear stop bits */
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uart->cr2.bit.stop = 0;
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@ -330,7 +339,10 @@ static const struct uart_stm32_config uart_stm32_dev_cfg_0 = {
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},
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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.clock_subsys = UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_USART1),
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#endif /* CONFIG_SOC_SERIES_STM32F1X */
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#elif CONFIG_SOC_SERIES_STM32F4X
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.pclken = { .bus = STM32F4X_CLOCK_BUS_APB2,
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.enr = STM32F4X_CLOCK_ENABLE_USART1 },
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#endif /* CONFIG_SOC_SERIES_STM32FX */
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};
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static struct uart_stm32_data uart_stm32_dev_data_0 = {
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@ -348,6 +360,8 @@ static void uart_stm32_irq_config_func_0(struct device *dev)
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{
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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#define PORT_0_IRQ STM32F1_IRQ_USART1
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#elif CONFIG_SOC_SERIES_STM32F4X
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#define PORT_0_IRQ STM32F4_IRQ_USART1
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#endif
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IRQ_CONNECT(PORT_0_IRQ,
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CONFIG_UART_STM32_PORT_0_IRQ_PRI,
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@ -374,7 +388,10 @@ static const struct uart_stm32_config uart_stm32_dev_cfg_1 = {
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},
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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.clock_subsys = UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_USART2),
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#endif /* CONFIG_SOC_SERIES_STM32F1X */
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#elif CONFIG_SOC_SERIES_STM32F4X
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.pclken = { .bus = STM32F4X_CLOCK_BUS_APB1,
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.enr = STM32F4X_CLOCK_ENABLE_USART2 },
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#endif /* CONFIG_SOC_SERIES_STM32FX */
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};
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static struct uart_stm32_data uart_stm32_dev_data_1 = {
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@ -392,6 +409,8 @@ static void uart_stm32_irq_config_func_1(struct device *dev)
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{
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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#define PORT_1_IRQ STM32F1_IRQ_USART2
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#elif CONFIG_SOC_SERIES_STM32F4X
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#define PORT_1_IRQ STM32F4_IRQ_USART2
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#endif
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IRQ_CONNECT(PORT_1_IRQ,
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CONFIG_UART_STM32_PORT_1_IRQ_PRI,
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@ -418,7 +437,9 @@ static const struct uart_stm32_config uart_stm32_dev_cfg_2 = {
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},
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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.clock_subsys = UINT_TO_POINTER(STM32F10X_CLOCK_SUBSYS_USART3),
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#endif /* CONFIG_SOC_SERIES_STM32F1X */
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#elif CONFIG_SOC_SERIES_STM32F4X
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.clock_subsys = UINT_TO_POINTER(STM32F40X_CLOCK_SUBSYS_USART3),
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#endif /* CONFIG_SOC_SERIES_STM32F4X */
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};
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static struct uart_stm32_data uart_stm32_dev_data_2 = {
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@ -436,6 +457,8 @@ static void uart_stm32_irq_config_func_2(struct device *dev)
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{
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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#define PORT_2_IRQ STM32F1_IRQ_USART3
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#elif CONFIG_SOC_SERIES_STM32F4X
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#define PORT_2_IRQ STM32F4_IRQ_USART3
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#endif
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IRQ_CONNECT(PORT_2_IRQ,
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CONFIG_UART_STM32_PORT_2_IRQ_PRI,
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@ -84,7 +84,12 @@ union __cr1 {
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uint32_t wake :1 __packed;
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uint32_t m :1 __packed;
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uint32_t ue :1 __packed;
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#ifdef CONFIG_SOC_SERIES_SOC32F1X
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uint32_t rsvd__14_15 :2 __packed;
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#elif CONFIG_SOC_SERIES_SOC32F4X
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uint32_t rsvd__14 :1 __packed;
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uint32_t over8 :1 __packed;
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#endif
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uint32_t rsvd__16_31 :16 __packed;
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} bit;
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};
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@ -123,7 +128,12 @@ union __cr3 {
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uint32_t rtse :1 __packed;
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uint32_t ctse :1 __packed;
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uint32_t ctsie :1 __packed;
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#ifdef CONFIG_SOC_SERIES_SOC32F1X
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uint32_t rsvd__11_31 :21 __packed;
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#elif CONFIG_SOC_SERIES_SOC32F4X
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uint32_t onebit :1 __packed;
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uint32_t rsvd__12_31 :20 __packed;
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#endif
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} bit;
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};
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@ -152,7 +162,11 @@ struct uart_stm32 {
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struct uart_stm32_config {
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struct uart_device_config uconf;
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/* clock subsystem driving this peripheral */
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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clock_control_subsys_t clock_subsys;
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#elif CONFIG_SOC_SERIES_STM32F4X
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struct stm32f4x_pclken pclken;
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#endif
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};
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/* driver data */
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