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uart: Enable QMSI driver for Quark D2000

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This patch fixes the QMSI UART shim driver so we are able to use it in
Quark D2000 based platforms. Differently from Quark SE, the peripheral
clock gate bit (CLK_PERIPH_CLK) is not enabled by default in Quark
D2000. We have to explicitly set this bit in order to properly initialize
the device.

Since this drivers is now properly working on Quark D2000, this patch
also sets the QMSI driver default options in arch/x86/soc/quark_d2000/
Kconfig.

Change-Id: I817b7703554be162ac628dcd8d3d07512b9eb3f5
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
This commit is contained in:
Andre Guedes 2016-03-18 17:02:07 -03:00 • committed by Gerrit Code Review
commit ace49af6b0
2 changed files with 17 additions and 2 deletions
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15
arch/x86/soc/quark_d2000/Kconfig
View file

@ -123,6 +123,21 @@ endif # UART_NS16550_PORT_1
endif # UART_NS16550
if UART_QMSI
config UART_QMSI_0
def_bool y
config UART_QMSI_0_IRQ
default 8
config UART_QMSI_0_IRQ_PRI
default 0
config UART_QMSI_1
def_bool y
config UART_QMSI_1_IRQ
default 6
config UART_QMSI_1_IRQ_PRI
default 0
endif # UART_QMSI
if UART_CONSOLE
config UART_CONSOLE_ON_DEV_NAME

4
drivers/serial/uart_qmsi.c
View file

@ -62,7 +62,7 @@ static void irq_config_func_0(struct device *dev);
static struct uart_qmsi_config_info config_info_0 = {
.instance = QM_UART_0,
.clock_gate = CLK_PERIPH_UARTA_REGISTER,
.clock_gate = CLK_PERIPH_UARTA_REGISTER | CLK_PERIPH_CLK,
.baud_divisor = QM_UART_CFG_BAUD_DL_PACK(
DIVISOR_HIGH(CONFIG_UART_QMSI_0_BAUDRATE),
DIVISOR_LOW(CONFIG_UART_QMSI_0_BAUDRATE),
@ -86,7 +86,7 @@ static void irq_config_func_1(struct device *dev);
static struct uart_qmsi_config_info config_info_1 = {
.instance = QM_UART_1,
.clock_gate = CLK_PERIPH_UARTB_REGISTER,
.clock_gate = CLK_PERIPH_UARTB_REGISTER | CLK_PERIPH_CLK,
.baud_divisor = QM_UART_CFG_BAUD_DL_PACK(
DIVISOR_HIGH(CONFIG_UART_QMSI_1_BAUDRATE),
DIVISOR_LOW(CONFIG_UART_QMSI_1_BAUDRATE),