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arm/nordic: use a common header for the nrf51/nrf52 SoC families

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Integrating the IRQ definitions for both nRF51 and nRF52, and defining
the set of IRQ values that are common to both.

Also switch the controller, uart and clock drivers to use the common
header definitions.

Change-Id: Id6816d7a97720896cfe4df83656fb8b1f8fb01fa
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
This commit is contained in:
Ricardo Salveti 2016-10-05 18:09:51 -03:00 • committed by Anas Nashif
commit 69b9451af1
7 changed files with 92 additions and 81 deletions
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74
arch/arm/soc/nordic_nrf5/include/nrf5_common.h Normal file
View file

@ -0,0 +1,74 @@
/*
* Copyright (c) 2016 Linaro Ltd.
* Copyright (c) 2016 Nordic Semiconductor ASA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _NRF5_SOC_COMMON_H_
#define _NRF5_SOC_COMMON_H_
/**
* @file Common definitions for NRF51/NRF52 family processors.
*
* The nRF51 IRQs can all be represented by the common definitions.
*
* Based on Nordic MDK included header files: nrf51.h and nrf51_to_nrf52.h
*/
#define NRF5_IRQ_POWER_CLOCK_IRQn 0
#define NRF5_IRQ_RADIO_IRQn 1
#define NRF5_IRQ_UART0_IRQn 2
#define NRF5_IRQ_SPI0_TWI0_IRQn 3
#define NRF5_IRQ_SPI1_TWI1_IRQn 4
#define NRF5_IRQ_GPIOTE_IRQn 6
#define NRF5_IRQ_ADC_IRQn 7
#define NRF5_IRQ_TIMER0_IRQn 8
#define NRF5_IRQ_TIMER1_IRQn 9
#define NRF5_IRQ_TIMER2_IRQn 10
#define NRF5_IRQ_RTC0_IRQn 11
#define NRF5_IRQ_TEMP_IRQn 12
#define NRF5_IRQ_RNG_IRQn 13
#define NRF5_IRQ_ECB_IRQn 14
#define NRF5_IRQ_CCM_AAR_IRQn 15
#define NRF5_IRQ_WDT_IRQn 16
#define NRF5_IRQ_RTC1_IRQn 17
#define NRF5_IRQ_QDEC_IRQn 18
#define NRF5_IRQ_LPCOMP_IRQn 19
#define NRF5_IRQ_SWI0_IRQn 20
#define NRF5_IRQ_SWI1_IRQn 21
#define NRF5_IRQ_SWI2_IRQn 22
#define NRF5_IRQ_SWI3_IRQn 23
#define NRF5_IRQ_SWI4_IRQn 24
#define NRF5_IRQ_SWI5_IRQn 25
/**
* @file Interrupt numbers for NRF52 family processors.
*
* Based on Nordic MDK included header file: nrf52.h
*/
#define NRF52_IRQ_NFCT_IRQn 5
#define NRF52_IRQ_TIMER3_IRQn 26
#define NRF52_IRQ_TIMER4_IRQn 27
#define NRF52_IRQ_PWM0_IRQn 28
#define NRF52_IRQ_PDM_IRQn 29
#define NRF52_IRQ_MWU_IRQn 32
#define NRF52_IRQ_PWM1_IRQn 33
#define NRF52_IRQ_PWM2_IRQn 34
#define NRF52_IRQ_SPIM2_SPIS2_SPI2_IRQn 35
#define NRF52_IRQ_RTC2_IRQn 36
#define NRF52_IRQ_I2S_IRQn 37
#define NRF52_IRQ_FPU_IRQn 38
#endif /* _NRF5_SOC_COMMON_H_ */

2
arch/arm/soc/nordic_nrf5/nrf52/Makefile
View file

@ -1,3 +1,5 @@
ZEPHYRINCLUDE += -I$(srctree)/arch/arm/soc/nordic_nrf5/include
ifdef CONFIG_SOC_SERIES_NRF52X
soc-cflags += -DNRF52
endif

2
arch/arm/soc/nordic_nrf5/nrf52/soc.h
View file

@ -23,7 +23,7 @@
#ifndef _ASMLANGUAGE
#include "soc_irq.h"
#include <nrf5_common.h>
#include <nrf.h>
#include <device.h>
#include <misc/util.h>

65
arch/arm/soc/nordic_nrf5/nrf52/soc_irq.h
View file

@ -1,65 +0,0 @@
/*
* Copyright (c) 2016 Nordic Semiconductor ASA
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file Interrupt numbers for NRF52 family processors.
*
* Based on Nordic MDK included header file: nrf52.h
*/
#ifndef _NRF52_SOC_IRQ_H_
#define _NRF52_SOC_IRQ_H_
#define NRF52_IRQ_POWER_CLOCK_IRQn 0
#define NRF52_IRQ_RADIO_IRQn 1
#define NRF52_IRQ_UARTE0_UART0_IRQn 2
#define NRF52_IRQ_SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn 3
#define NRF52_IRQ_SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn 4
#define NRF52_IRQ_NFCT_IRQn 5
#define NRF52_IRQ_GPIOTE_IRQn 6
#define NRF52_IRQ_SAADC_IRQn 7
#define NRF52_IRQ_TIMER0_IRQn 8
#define NRF52_IRQ_TIMER1_IRQn 9
#define NRF52_IRQ_TIMER2_IRQn 10
#define NRF52_IRQ_RTC0_IRQn 11
#define NRF52_IRQ_TEMP_IRQn 12
#define NRF52_IRQ_RNG_IRQn 13
#define NRF52_IRQ_ECB_IRQn 14
#define NRF52_IRQ_CCM_AAR_IRQn 15
#define NRF52_IRQ_WDT_IRQn 16
#define NRF52_IRQ_RTC1_IRQn 17
#define NRF52_IRQ_QDEC_IRQn 18
#define NRF52_IRQ_COMP_LPCOMP_IRQn 19
#define NRF52_IRQ_SWI0_EGU0_IRQn 20
#define NRF52_IRQ_SWI1_EGU1_IRQn 21
#define NRF52_IRQ_SWI2_EGU2_IRQn 22
#define NRF52_IRQ_SWI3_EGU3_IRQn 23
#define NRF52_IRQ_SWI4_EGU4_IRQn 24
#define NRF52_IRQ_SWI5_EGU5_IRQn 25
#define NRF52_IRQ_TIMER3_IRQn 26
#define NRF52_IRQ_TIMER4_IRQn 27
#define NRF52_IRQ_PWM0_IRQn 28
#define NRF52_IRQ_PDM_IRQn 29
#define NRF52_IRQ_MWU_IRQn 32
#define NRF52_IRQ_PWM1_IRQn 33
#define NRF52_IRQ_PWM2_IRQn 34
#define NRF52_IRQ_SPIM2_SPIS2_SPI2_IRQn 35
#define NRF52_IRQ_RTC2_IRQn 36
#define NRF52_IRQ_I2S_IRQn 37
#define NRF52_IRQ_FPU_IRQn 38
#endif /* _NRF52_SOC_IRQ_H_ */

24
drivers/bluetooth/controller/hci/hci_driver.c
View file

@ -112,12 +112,12 @@ static void rng_nrf5_isr(void *arg)
static void swi4_nrf5_isr(void *arg)
{
work_run(NRF52_IRQ_SWI4_EGU4_IRQn);
work_run(NRF5_IRQ_SWI4_IRQn);
}
static void swi5_nrf5_isr(void *arg)
{
work_run(NRF52_IRQ_SWI5_EGU5_IRQn);
work_run(NRF5_IRQ_SWI5_IRQn);
}
static void recv_fiber(int unused0, int unused1)
@ -300,16 +300,16 @@ static int hci_driver_open(void)
return -ENOMEM;
}
IRQ_CONNECT(NRF52_IRQ_RADIO_IRQn, 0, radio_nrf5_isr, 0, 0);
IRQ_CONNECT(NRF52_IRQ_RTC0_IRQn, 0, rtc0_nrf5_isr, 0, 0);
IRQ_CONNECT(NRF52_IRQ_RNG_IRQn, 1, rng_nrf5_isr, 0, 0);
IRQ_CONNECT(NRF52_IRQ_SWI4_EGU4_IRQn, 0, swi4_nrf5_isr, 0, 0);
IRQ_CONNECT(NRF52_IRQ_SWI5_EGU5_IRQn, 1, swi5_nrf5_isr, 0, 0);
irq_enable(NRF52_IRQ_RADIO_IRQn);
irq_enable(NRF52_IRQ_RTC0_IRQn);
irq_enable(NRF52_IRQ_RNG_IRQn);
irq_enable(NRF52_IRQ_SWI4_EGU4_IRQn);
irq_enable(NRF52_IRQ_SWI5_EGU5_IRQn);
IRQ_CONNECT(NRF5_IRQ_RADIO_IRQn, 0, radio_nrf5_isr, 0, 0);
IRQ_CONNECT(NRF5_IRQ_RTC0_IRQn, 0, rtc0_nrf5_isr, 0, 0);
IRQ_CONNECT(NRF5_IRQ_RNG_IRQn, 1, rng_nrf5_isr, 0, 0);
IRQ_CONNECT(NRF5_IRQ_SWI4_IRQn, 0, swi4_nrf5_isr, 0, 0);
IRQ_CONNECT(NRF5_IRQ_SWI5_IRQn, 1, swi5_nrf5_isr, 0, 0);
irq_enable(NRF5_IRQ_RADIO_IRQn);
irq_enable(NRF5_IRQ_RTC0_IRQn);
irq_enable(NRF5_IRQ_RNG_IRQn);
irq_enable(NRF5_IRQ_SWI4_IRQn);
irq_enable(NRF5_IRQ_SWI5_IRQn);
nano_sem_init(&nano_sem_recv);
fiber_start(recv_fiber_stack, sizeof(recv_fiber_stack),

2
drivers/clock_control/nrf5_power_clock.c
View file

@ -308,7 +308,7 @@ static int _clock_control_init(struct device *dev)
* power peripheral driver and/or new SoC series.
* NOTE: Currently the operations here are idempotent.
*/
IRQ_CONNECT(NRF52_IRQ_POWER_CLOCK_IRQn,
IRQ_CONNECT(NRF5_IRQ_POWER_CLOCK_IRQn,
CONFIG_CLOCK_CONTROL_NRF5_IRQ_PRIORITY,
_power_clock_isr, 0, 0);

4
drivers/serial/uart_nrf5.c
View file

@ -459,10 +459,10 @@ DEVICE_INIT(uart_nrf5_0, CONFIG_UART_NRF5_NAME, &uart_nrf5_init,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_nrf5_irq_config(struct device *port)
{
IRQ_CONNECT(NRF52_IRQ_UARTE0_UART0_IRQn,
IRQ_CONNECT(NRF5_IRQ_UART0_IRQn,
CONFIG_UART_NRF5_IRQ_PRI,
uart_nrf5_isr, DEVICE_GET(uart_nrf5_0),
0);
irq_enable(NRF52_IRQ_UARTE0_UART0_IRQn);
irq_enable(NRF5_IRQ_UART0_IRQn);
}
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */