Commit graph

1403 commits

Author SHA1 Message Date
Jun Yang
27d8329fc9 clock/usdhc: Enable clock of USDHC of i.MXRT
Enable clock of USDHC of i.MXRT.

Add clock interface for USDHC in ccm.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-10 11:58:15 -05:00
Jun Yang
6ff5ac05e4 usdhc/pinmux: configure pinmux of usdhc on mimxrt1050 evk
Implementation of pinmux of usdhc depends on board design.

Usdhc driver could change pinmux according to SD mode, SoC

should provide API for this. Board pinmux should register

its pinmux function to SoC.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-10 11:58:15 -05:00
Jun Yang
c6864dbea3 Kconfig: Kconfig support i.MX RT USDHC
Add Kconifg options to support i.MXRT USDHC driver.

Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-10 11:58:15 -05:00
Francois Ramu
26c38a49a2 soc: arm: uart: Add STM32G0X UART support
Add UART support for STM32G0X SoC series.

Signed-off-by: Philippe Retornaz <philippe@shapescale.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2019-07-05 10:35:55 -05:00
Francois Ramu
f9d2a41612 drivers: interrupt_controller: Add STM32G0X interrupt support
Add interrupt support for STM32G0X SoC series.

Signed-off-by: Philippe Retornaz <philippe@shapescale.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>

# Conflicts:
#	drivers/interrupt_controller/exti_stm32.c
2019-07-05 10:35:55 -05:00
Francois Ramu
dd3ee06af7 drivers: gpio: Add STM32G0X pinmux support
Add gpio support for STM32G0X SoC series.

Signed-off-by: Philippe Retornaz <philippe@shapescale.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>

# Conflicts:
#	drivers/gpio/gpio_stm32.h
2019-07-05 10:35:55 -05:00
Francois Ramu
da48451a01 drivers: pwm: Add STM32G0XX pwm support
Add pwm support for STM32G0X SoC series.

Signed-off-by: Philippe Retornaz <philippe@shapescale.com
Signed-off-by: Francois Ramu <francois.ramu@st.com>
2019-07-05 10:35:55 -05:00
Francois Ramu
bfc2ea6dd5 drivers: flash: Add STM32G0XX flash support
Add flash support for STM32G0X SoC series.

Signed-off-by: Philippe Retornaz <philippe@shapescale.com
Signed-off-by: Francois Ramu <francois.ramu@st.com>
2019-07-05 10:35:55 -05:00
Francois Ramu
7ea00134f5 soc: arm: st_stm32: Add STM32G071 SoC series
This patch adds support for the STM32G071xx
 from STMicroelectronics.

Signed-off-by: Philippe Retornaz <philippe@shapescale.com>
Signed-off-by: Francois Ramu <francois.ramu@st.com>
2019-07-05 10:35:55 -05:00
Erwan Gouriou
0914f1031d drivers/gpio: stm32: Add semaphore on gpio_configure
Protect gpio_configure function in dual core context.
This operation is not needed for other fuctions of the api:
* init
* read
* write

Protecting gpio_configure also protects access to
interrupt_controller IP.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-04 08:50:04 -04:00
Erwan Gouriou
141b6500c9 soc: stm32h7: Add support for Cortex-M4 core
Add support for C-M4 core on STM32H7 series.
It is enabled in Dual core context with 2 alternatives boot methods:
* Boot CM4 CM7: Both core boot at reset, then CM4 enters Stop mode.
CM7 performs system configuration then finally wakes up CM4
* Boot CM7, CM4 Gated: Only CM7 boots at reset. Once done with
system configuration it triggers (requires option byte update)

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-04 08:50:04 -04:00
Erwan Gouriou
fda2ea7253 drivers/serial: stm32: Add support for STM32H7 series
Add needful to enable uart on STM32H7.
This mostly impact dts but as well soc for fixup.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-04 08:50:04 -04:00
Erwan Gouriou
d185ec4cff drivers/gpio: Add support on STM32H7 series
Add GPIO support on STM32H7.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-04 08:50:04 -04:00
Erwan Gouriou
80278f7a48 drivers/interrupt_controller: stm32: Add support for stm32h7
Add bare minimum to enable EXTI on STM32H7,
in single core configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-04 08:50:04 -04:00
Erwan Gouriou
2805ea9193 drivers/clock_control: STM32H7 support
Provide basic clock control driver for STM32H7.
Bus clock activation is done through CM7 and CM4 common registers
so we don't have to care to the CPU Id before accessing.
Accesses are not protected for now. Only possible configuration
is system clock source set to HSE driven PLL.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-04 08:50:04 -04:00
Erwan Gouriou
ef35fbcf42 soc/arm: Provide basic support for STM32H7 series
Enable basic support to STM32H7, in single core configuration (M7).

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-04 08:50:04 -04:00
Charles E. Youse
7c2d7d7b69 arch/x86: move arch/x86/include/mmustructs.h to ia32/mmustructs.h
For now, only the 32-bit subarchitecture supports memory protection.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-03 20:01:17 -04:00
Andy Ross
05c8e05634 soc/arm: Remove 1 kHz tick rate default for mcimx7_m4 and msp432p401r
As with the STM32 boards, these had an existing default for tick rate
that is now lower than the 10 kHz default.  They're SysTick devices
that can handle the higher rate just fine.  Use that.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-07-02 22:52:29 -04:00
Andy Ross
7c0f44816e soc/arm: Increase nRF timer default to the cycle rate.
The nRF timer runs at only 32 kHz, so there's little reason to try to
divide it to get a synthesized tick rate.  Just use the raw clock as
the tick rate, which provides maximal precision and very
singnificantly simplifies the generated code for the ISR.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-07-02 22:52:29 -04:00
Erwan Gouriou
f5b375062c soc: stm32f7: Fix fixup file for uart devices
UART related defines in STM32F7 files where filled with
references to USART.
Instances 4, 5, 7 and 8 of SoC serial port are actually UARTs.
So rename define's accordingly. Otherwise it couldn't build.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-02 20:27:22 -04:00
Charles E. Youse
0325a3d972 arch/x86: eliminate include/arch/x86/irq_controller.h
The MVIC is no longer supported, and only the APIC-based interrupt
subsystem remains. Thus this layer of indirection is unnecessary.

This also corrects an oversight left over from the Jailhouse x2APIC
implementation affecting EOI delivery for direct ISRs only.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-02 19:30:00 -04:00
Charles E. Youse
7f0ab527e3 arch/x86: move 32-bit linker script to ia32/ directory
No functional changes. All references in soc/ are updated.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-02 19:30:00 -04:00
Charles E. Youse
6f3009ecf0 arch/x86: move include/arch/x86/asm.h to include/arch/x86/ia32/asm.h
This file is 32-bit specific, so it is moved into the ia32/ directory
and references to it are updated accordingly.

Also, SP_ARG* definitions are no longer used, so they are removed.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-02 19:30:00 -04:00
Ioannis Glaropoulos
d202d620c7 soc: nordic: nrf9160: add IPC capabilities
The IPC peripheral is missing from the list of
supported HW for nRF9160, so this commit adds
that.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-07-02 19:09:25 -04:00
Henrik Brix Andersen
56940ac239 soc: arm: nxp: ke1xf: add watchdog support
Add watchdog (WDOG32) support to the NXP Kinetis KE1xF SoC series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2019-07-02 18:00:16 -05:00
Kumar Gala
502094b096 arm: mps_an521: Add support for the AN521 on MPS2+
The AN521 is a Soft Macro Model implementation of the SSE-200 subsystem
with SIE-200 and CMSDK components targeting the MPS2+ board. The
SSE-200 subsystem implements two Cortex-M33 cores.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
2019-07-02 17:44:25 -05:00
Loic Poulain
050a715d21 soc: nxp: rt: Enable mcux gpt when counter is enabled
Enable NXP MCUX driver and devices when counter config is selected.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-07-01 11:53:07 -05:00
Loic Poulain
304c5fd196 dts: arm: nxp_rt: Add GPT nodes
i.MX RT chips have two GPT modules.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-07-01 11:53:07 -05:00
Loic Poulain
517ef0d688 soc: nxp:rt: Add HAS_MCUX_GPT flag
For RT SOCs with General Purporse Timer module(s) (GPT).

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-07-01 11:53:07 -05:00
Anas Nashif
a2fd7d70ec cleanup: include/: move misc/util.h to sys/util.h
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif
536dd5a71f cleanup: include/: move misc/slist.h to sys/slist.h
move misc/slist.h to sys/slist.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif
9ab2a56751 cleanup: include/: move misc/printk.h to sys/printk.h
move misc/printk.h to sys/printk.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif
5eb90ec169 cleanup: include/: move misc/__assert.h to sys/__assert.h
move misc/__assert.h to sys/__assert.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif
d1b2718687 cleanup: include/: move uart.h to drivers/uart.h
move uart.h to drivers/uart.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif
6524925753 cleanup: include/: move ipm.h to drivers/ipm.h
move ipm.h to drivers/ipm.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif
ef281c4237 cleanup: include/: move sys_io.h to sys/sys_io.h
move sys_io.h to sys/sys_io.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif
190e368275 cleanup: include/: move power.h to power/power.h
move power.h to power/power.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif
10291a0789 cleanup: include/: move tracing.h to debug/tracing.h
move tracing.h to debug/tracing.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Daniel Leung
06a3735754 x86_64: minimally preparing for enabling newlib
The libc hooks for Newlib requires CONFIG_SRAM_SIZE and
the symbol "_end" at the end of memory. This is in preparation
for enabling Newlib for x86_64.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-06-27 16:08:32 -04:00
Alexander Wachter
14e31ba419 soc: nxp: k6x: Add CAN support
This commit adds CAN support for Kinetis K6x family.

Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
2019-06-26 16:05:51 -05:00
Wayne Ren
54b229fc42 soc: arc: optmize and bug fix the compile options
* when -mcpu is given, e.g. -mcpu=em4_dmips,-mnorm,-mdiv_em
etc. are already given, no need to duplicate

* use zephyr_compiler_options to replace zephyr_cc_option
zephyr_cc_option will do compile option check first then add
the checked options into option list. It's too strict that makes
options like -mfpu, -mmpy-option cannot be added.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-06-26 09:10:44 -04:00
Wayne Ren
27fbe34718 soc: nsim: nsim em targets are EM4_FPUDA
the nsim em targets in zephyr are configured
as EM4_FPUDA

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-06-26 09:10:44 -04:00
Anas Nashif
43a49335f4 include: move interrupt controller headers to interrupt_controller/
Move internal and architecture specific headers from include/drivers to
subfolder for interrupt_controller:

include/drivers/interrupt_controller/

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-25 15:27:00 -04:00
Charles E. Youse
57b46bbc85 soc/x86/intel_quark: remove support for Quark D2000 SoC
Removed Quark D2000 SoC files and first-order related DT bindings.

A few config options have been moved from the CONFIG_* space to
the DT_* space, as they were defined in the D2000 Kconfig files
and "leaked" into the other Quark trees.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-25 08:06:43 -04:00
Henrik Brix Andersen
52cfe30d5e soc: nxp: ke1xf: add CAN support
Add support for the FlexCAN controllers found in the NXP Kinetis KE1xF
SoC series.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2019-06-24 14:33:46 -05:00
Henrik Brix Andersen
b5e3be9e8a soc: arm: nxp: ke1xf: enable MCUX SCG clock controller driver
Enable the MCUX SCG clock controller driver by default for the NXP
Kinetis KE1xF SoC series. Move the generic CLKOUT configuration from
SoC to the clock controller driver.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2019-06-24 14:33:46 -05:00
Henrik Brix Andersen
dded1d076a dts: can: allow individual specification of prop seg and phase seg1 quanta
Allow individual specification of the time quanta used for the CAN bus
propagation segment and phase segment 1.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2019-06-24 14:33:46 -05:00
Erwan Gouriou
9f857c3ba8 soc: stm32f3: Delete obsolete FLASH_PAGE_SIZE Kconfig symbol
Definition of obsolete FLASH_PAGE_SIZE Kconfig symbol was
remaining in STM32F3 soc files.
Clean these.


Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-06-24 07:23:11 -04:00
Andrei Gansari
58e05ddcc1 drivers: uart for LPC devices interrupt enabled
NXP's MCU LPC families uart interrupt was enabled.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2019-06-21 11:24:09 -05:00
Anas Nashif
f2cb20c772 docs: fix misspelling across the tree
Found a few annoying typos and figured I better run script and
fix anything it can find, here are the results...

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-19 15:34:13 -05:00