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soc: nuvoton: numaker: add support for m55m1x series

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Add initial support for nuvoton numaker m55m1x SoC series
including basic init and device tree source include.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
This commit is contained in:
cyliang tw 2025-02-20 14:48:02 +08:00 • committed by Fabio Baltieri
commit 47dfd857f9
15 changed files with 1329 additions and 0 deletions
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35
dts/arm/nuvoton/m55m1h2l.dtsi Normal file
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/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <nuvoton/m55m1x.dtsi>
/ {
sram0: memory@20100000 {
compatible = "mmio-sram";
reg = <0x20100000 DT_SIZE_K(1344)>;
};
dtcm: memory@20000000 {
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "DTCM";
};
itcm: memory@0 {
compatible = "zephyr,memory-region", "arm,itcm";
reg = <0x00000000 DT_SIZE_K(64)>;
zephyr,memory-region = "ITCM";
};
soc {
fmc: flash-controller@40044000 {
flash0: flash@100000 {
reg = <0x100000 DT_SIZE_K(2048)>;
};
};
};
};

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dts/arm/nuvoton/m55m1x.dtsi Normal file
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/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv8.1-m.dtsi>
#include <mem.h>
#include <freq.h>
#include <zephyr/dt-bindings/clock/numaker_m55m1x_clock.h>
#include <zephyr/dt-bindings/reset/numaker_m55m1x_reset.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
/ {
chosen {
zephyr,flash-controller = &fmc;
};
aliases {
rtc = &rtc;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m55";
reg = <0>;
};
};
sysclk: system-clock {
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(220)>;
#clock-cells = <0>;
};
soc {
scc: system-clock-controller@40001000 {
compatible = "nuvoton,numaker-scc";
reg = <0x40001000 0x100>;
#clock-cells = <0>;
lxt = "enable";
clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_PCLK0DIV(2) |
NUMAKER_CLK_PCLKDIV_PCLK1DIV(2) |
NUMAKER_CLK_PCLKDIV_PCLK2DIV(2) |
NUMAKER_CLK_PCLKDIV_PCLK3DIV(2) |
NUMAKER_CLK_PCLKDIV_PCLK4DIV(2))>;
core-clock = <DT_FREQ_M(220)>;
powerdown-mode = <NUMAKER_PMC_SPD0>;
pcc: peripheral-clock-controller {
compatible = "nuvoton,numaker-pcc";
#clock-cells = <3>;
};
};
rst: reset-controller@40000000 {
compatible = "nuvoton,numaker-rst";
reg = <0x40000000 0x2e0>;
#reset-cells = <1>;
};
fmc: flash-controller@40044000 {
compatible = "nuvoton,numaker-fmc";
reg = <0x40044000 0x120>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@100000 {
compatible = "soc-nv-flash";
erase-block-size = <8192>;
write-block-size = <4>;
};
};
uart0: serial@4024d000 {
compatible = "nuvoton,numaker-uart";
reg = <0x4024d000 0x1000>;
interrupts = <75 0>;
resets = <&rst NUMAKER_SYS_UART0RST>;
clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_UARTSEL0_UART0SEL_HIRC
NUMAKER_CLK_UARTDIV0_UART0DIV(1)>;
status = "disabled";
};
uart1: serial@4028d000 {
compatible = "nuvoton,numaker-uart";
reg = <0x4028d000 0x1000>;
interrupts = <76 0>;
resets = <&rst NUMAKER_SYS_UART1RST>;
clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_UARTSEL0_UART1SEL_HIRC
NUMAKER_CLK_UARTDIV0_UART1DIV(1)>;
status = "disabled";
};
uart2: serial@4024e000 {
compatible = "nuvoton,numaker-uart";
reg = <0x4024e000 0x1000>;
interrupts = <77 0>;
resets = <&rst NUMAKER_SYS_UART2RST>;
clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_UARTSEL0_UART2SEL_HIRC
NUMAKER_CLK_UARTDIV0_UART2DIV(1)>;
status = "disabled";
};
uart3: serial@4028e000 {
compatible = "nuvoton,numaker-uart";
reg = <0x4028e000 0x1000>;
interrupts = <78 0>;
resets = <&rst NUMAKER_SYS_UART3RST>;
clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_UARTSEL0_UART3SEL_HIRC
NUMAKER_CLK_UARTDIV0_UART3DIV(1)>;
status = "disabled";
};
uart4: serial@4024f000 {
compatible = "nuvoton,numaker-uart";
reg = <0x4024f000 0x1000>;
interrupts = <79 0>;
resets = <&rst NUMAKER_SYS_UART4RST>;
clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_UARTSEL0_UART4SEL_HIRC
NUMAKER_CLK_UARTDIV0_UART4DIV(1)>;
status = "disabled";
};
uart5: serial@4028f000 {
compatible = "nuvoton,numaker-uart";
reg = <0x4028f000 0x1000>;
interrupts = <80 0>;
resets = <&rst NUMAKER_SYS_UART5RST>;
clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_UARTSEL0_UART5SEL_HIRC
NUMAKER_CLK_UARTDIV0_UART5DIV(1)>;
status = "disabled";
};
uart6: serial@40250000 {
compatible = "nuvoton,numaker-uart";
reg = <0x40250000 0x1000>;
interrupts = <81 0>;
resets = <&rst NUMAKER_SYS_UART6RST>;
clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_UARTSEL0_UART6SEL_HIRC
NUMAKER_CLK_UARTDIV0_UART6DIV(1)>;
status = "disabled";
};
uart7: serial@40290000 {
compatible = "nuvoton,numaker-uart";
reg = <0x40290000 0x1000>;
interrupts = <82 0>;
resets = <&rst NUMAKER_SYS_UART7RST>;
clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_UARTSEL0_UART7SEL_HIRC
NUMAKER_CLK_UARTDIV0_UART7DIV(1)>;
status = "disabled";
};
uart8: serial@40251000 {
compatible = "nuvoton,numaker-uart";
reg = <0x40251000 0x1000>;
interrupts = <83 0>;
resets = <&rst NUMAKER_SYS_UART8RST>;
clocks = <&pcc NUMAKER_UART8_MODULE NUMAKER_CLK_UARTSEL1_UART8SEL_HIRC
NUMAKER_CLK_UARTDIV1_UART8DIV(1)>;
status = "disabled";
};
uart9: serial@40291000 {
compatible = "nuvoton,numaker-uart";
reg = <0x40291000 0x1000>;
interrupts = <84 0>;
resets = <&rst NUMAKER_SYS_UART9RST>;
clocks = <&pcc NUMAKER_UART9_MODULE NUMAKER_CLK_UARTSEL1_UART9SEL_HIRC
NUMAKER_CLK_UARTDIV1_UART9DIV(1)>;
status = "disabled";
};
pinctrl: pin-controller@40000080 {
compatible = "nuvoton,numaker-pinctrl";
reg = <0x40000080 0x30
0x40000300 0x100>;
reg-names = "mfos", "mfp";
};
gpioa: gpio@40229000 {
compatible = "nuvoton,numaker-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40229000 0x40>;
clocks = <&pcc NUMAKER_GPIOA_MODULE 0 0>;
status = "disabled";
interrupts = <20 2>;
};
gpiob: gpio@40229040 {
compatible = "nuvoton,numaker-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40229040 0x40>;
clocks = <&pcc NUMAKER_GPIOB_MODULE 0 0>;
status = "disabled";
interrupts = <21 2>;
};
gpioc: gpio@40229080 {
compatible = "nuvoton,numaker-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40229080 0x40>;
clocks = <&pcc NUMAKER_GPIOC_MODULE 0 0>;
status = "disabled";
interrupts = <22 2>;
};
gpiod: gpio@402290c0 {
compatible = "nuvoton,numaker-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x402290c0 0x40>;
clocks = <&pcc NUMAKER_GPIOD_MODULE 0 0>;
status = "disabled";
interrupts = <23 2>;
};
gpioe: gpio@40229100 {
compatible = "nuvoton,numaker-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40229100 0x40>;
clocks = <&pcc NUMAKER_GPIOE_MODULE 0 0>;
status = "disabled";
interrupts = <24 2>;
};
gpiof: gpio@40229140 {
compatible = "nuvoton,numaker-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40229140 0x40>;
clocks = <&pcc NUMAKER_GPIOF_MODULE 0 0>;
status = "disabled";
interrupts = <25 2>;
};
gpiog: gpio@40229180 {
compatible = "nuvoton,numaker-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40229180 0x40>;
clocks = <&pcc NUMAKER_GPIOG_MODULE 0 0>;
status = "disabled";
interrupts = <26 2>;
};
gpioh: gpio@402291c0 {
compatible = "nuvoton,numaker-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x402291c0 0x40>;
clocks = <&pcc NUMAKER_GPIOH_MODULE 0 0>;
status = "disabled";
interrupts = <27 2>;
};
gpioi: gpio@40229200 {
compatible = "nuvoton,numaker-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40229200 0x40>;
clocks = <&pcc NUMAKER_GPIOI_MODULE 0 0>;
status = "disabled";
interrupts = <28 2>;
};
gpioj: gpio@40229240 {
compatible = "nuvoton,numaker-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40229240 0x40>;
clocks = <&pcc NUMAKER_GPIOJ_MODULE 0 0>;
status = "disabled";
interrupts = <29 2>;
};
rtc: rtc@40297000 {
compatible = "nuvoton,numaker-rtc";
reg = <0x40297000 0x1000>;
interrupts = <6 0>;
oscillator = "lxt";
clocks = <&pcc NUMAKER_RTC0_MODULE 0 0>;
alarms-count = <1>;
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};

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include/zephyr/dt-bindings/clock/numaker_m55m1x_clock.h Normal file
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/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M55M1X_CLOCK_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M55M1X_CLOCK_H
#define NUMAKER_CLK_SCLKSEL_SCLKSEL_HIRC 0x00000000
#define NUMAKER_CLK_SCLKSEL_SCLKSEL_MIRC 0x00000001
#define NUMAKER_CLK_SCLKSEL_SCLKSEL_HIRC48M 0x00000002
#define NUMAKER_CLK_SCLKSEL_SCLKSEL_HXT 0x00000003
#define NUMAKER_CLK_SCLKSEL_SCLKSEL_APLL0 0x00000004
#define NUMAKER_CLK_BPWMSEL_BPWM0SEL_PCLK0 0x00000000
#define NUMAKER_CLK_BPWMSEL_BPWM0SEL_HCLK0 0x00000001
#define NUMAKER_CLK_BPWMSEL_BPWM1SEL_PCLK2 0x00000000
#define NUMAKER_CLK_BPWMSEL_BPWM1SEL_HCLK0 0x00000010
#define NUMAKER_CLK_CANFDSEL_CANFD0SEL_HXT 0x00000000
#define NUMAKER_CLK_CANFDSEL_CANFD0SEL_APLL0_DIV2 0x00000001
#define NUMAKER_CLK_CANFDSEL_CANFD0SEL_HCLK0 0x00000002
#define NUMAKER_CLK_CANFDSEL_CANFD0SEL_HIRC 0x00000003
#define NUMAKER_CLK_CANFDSEL_CANFD0SEL_HIRC48M_DIV4 0x00000004
#define NUMAKER_CLK_CANFDSEL_CANFD1SEL_HXT 0x00000000
#define NUMAKER_CLK_CANFDSEL_CANFD1SEL_APLL0_DIV2 0x00000010
#define NUMAKER_CLK_CANFDSEL_CANFD1SEL_HCLK0 0x00000020
#define NUMAKER_CLK_CANFDSEL_CANFD1SEL_HIRC 0x00000030
#define NUMAKER_CLK_CANFDSEL_CANFD1SEL_HIRC48M_DIV4 0x00000040
#define NUMAKER_CLK_CCAPSEL_CCAP0SEL_MIRC 0x00000000
#define NUMAKER_CLK_CCAPSEL_CCAP0SEL_HCLK2 0x00000001
#define NUMAKER_CLK_CCAPSEL_CCAP0SEL_HIRC 0x00000002
#define NUMAKER_CLK_CCAPSEL_CCAP0SEL_APLL0_DIV2 0x00000003
#define NUMAKER_CLK_CCAPSEL_CCAP0SEL_HXT 0x00000004
#define NUMAKER_CLK_CLKOSEL_CLKOSEL_SYSCLK 0x00000000
#define NUMAKER_CLK_CLKOSEL_CLKOSEL_ACLK 0x00000001
#define NUMAKER_CLK_CLKOSEL_CLKOSEL_HCLK0 0x00000002
#define NUMAKER_CLK_CLKOSEL_CLKOSEL_HCLK1 0x00000003
#define NUMAKER_CLK_CLKOSEL_CLKOSEL_HCLK2 0x00000004
#define NUMAKER_CLK_CLKOSEL_CLKOSEL_APLL0_DIV2 0x00000005
#define NUMAKER_CLK_CLKOSEL_CLKOSEL_APLL1_DIV2 0x00000006
#define NUMAKER_CLK_CLKOSEL_CLKOSEL_HIRC48M 0x00000007
#define NUMAKER_CLK_CLKOSEL_CLKOSEL_HXT 0x00000008
#define NUMAKER_CLK_CLKOSEL_CLKOSEL_HIRC 0x00000009
#define NUMAKER_CLK_CLKOSEL_CLKOSEL_MIRC 0x0000000A
#define NUMAKER_CLK_CLKOSEL_CLKOSEL_LXT 0x0000000B
#define NUMAKER_CLK_CLKOSEL_CLKOSEL_LIRC 0x0000000C
#define NUMAKER_CLK_DMICSEL_DMIC0SEL_HXT 0x00000000
#define NUMAKER_CLK_DMICSEL_DMIC0SEL_APLL1_DIV2 0x00000001
#define NUMAKER_CLK_DMICSEL_DMIC0SEL_MIRC 0x00000002
#define NUMAKER_CLK_DMICSEL_DMIC0SEL_HIRC 0x00000003
#define NUMAKER_CLK_DMICSEL_DMIC0SEL_HIRC48M 0x00000004
#define NUMAKER_CLK_DMICSEL_DMIC0SEL_PCLK4 0x00000005
#define NUMAKER_CLK_DMICSEL_VAD0SEL_PCLK4 0x00000000
#define NUMAKER_CLK_DMICSEL_VAD0SEL_MIRC 0x00000010
#define NUMAKER_CLK_DMICSEL_VAD0SEL_HIRC 0x00000020
#define NUMAKER_CLK_EADCSEL_EADC0SEL_APLL1_DIV2 0x00000000
#define NUMAKER_CLK_EADCSEL_EADC0SEL_APLL0_DIV2 0x00000001
#define NUMAKER_CLK_EADCSEL_EADC0SEL_PCLK0 0x00000002
#define NUMAKER_CLK_EPWMSEL_EPWM0SEL_PCLK0 0x00000000
#define NUMAKER_CLK_EPWMSEL_EPWM0SEL_HCLK0 0x00000001
#define NUMAKER_CLK_EPWMSEL_EPWM1SEL_PCLK2 0x00000000
#define NUMAKER_CLK_EPWMSEL_EPWM1SEL_HCLK0 0x00000010
#define NUMAKER_CLK_FMCSEL_FMC0SEL_HIRC 0x00000000
#define NUMAKER_CLK_FMCSEL_FMC0SEL_HIRC48M_DIV4 0x00000001
#define NUMAKER_CLK_I2SSEL_I2S0SEL_HXT 0x00000000
#define NUMAKER_CLK_I2SSEL_I2S0SEL_APLL1_DIV2 0x00000001
#define NUMAKER_CLK_I2SSEL_I2S0SEL_APLL0_DIV2 0x00000002
#define NUMAKER_CLK_I2SSEL_I2S0SEL_PCLK1 0x00000003
#define NUMAKER_CLK_I2SSEL_I2S0SEL_HIRC 0x00000004
#define NUMAKER_CLK_I2SSEL_I2S0SEL_HIRC48M 0x00000005
#define NUMAKER_CLK_I2SSEL_I2S1SEL_HXT 0x00000000
#define NUMAKER_CLK_I2SSEL_I2S1SEL_APLL1_DIV2 0x00000010
#define NUMAKER_CLK_I2SSEL_I2S1SEL_APLL0_DIV2 0x00000020
#define NUMAKER_CLK_I2SSEL_I2S1SEL_PCLK3 0x00000030
#define NUMAKER_CLK_I2SSEL_I2S1SEL_HIRC 0x00000040
#define NUMAKER_CLK_I2SSEL_I2S1SEL_HIRC48M 0x00000050
#define NUMAKER_CLK_I3CSEL_I3C0SEL_HCLK0 0x00000000
#define NUMAKER_CLK_I3CSEL_I3C0SEL_APLL1 0x00000001
#define NUMAKER_CLK_KPISEL_KPI0SEL_HIRC48M_DIV4 0x00000000
#define NUMAKER_CLK_KPISEL_KPI0SEL_HIRC 0x00000001
#define NUMAKER_CLK_KPISEL_KPI0SEL_LIRC 0x00000002
#define NUMAKER_CLK_KPISEL_KPI0SEL_HXT 0x00000003
#define NUMAKER_CLK_LPADCSEL_LPADC0SEL_PCLK4 0x00000000
#define NUMAKER_CLK_LPADCSEL_LPADC0SEL_LXT 0x00000001
#define NUMAKER_CLK_LPADCSEL_LPADC0SEL_MIRC 0x00000002
#define NUMAKER_CLK_LPADCSEL_LPADC0SEL_HIRC 0x00000003
#define NUMAKER_CLK_LPSPISEL_LPSPI0SEL_PCLK4 0x00000000
#define NUMAKER_CLK_LPSPISEL_LPSPI0SEL_MIRC 0x00000001
#define NUMAKER_CLK_LPSPISEL_LPSPI0SEL_HIRC 0x00000002
#define NUMAKER_CLK_LPTMRSEL_LPTMR0SEL_PCLK4 0x00000000
#define NUMAKER_CLK_LPTMRSEL_LPTMR0SEL_LXT 0x00000001
#define NUMAKER_CLK_LPTMRSEL_LPTMR0SEL_LIRC 0x00000002
#define NUMAKER_CLK_LPTMRSEL_LPTMR0SEL_MIRC 0x00000003
#define NUMAKER_CLK_LPTMRSEL_LPTMR0SEL_HIRC 0x00000004
#define NUMAKER_CLK_LPTMRSEL_LPTMR0SEL_EXT 0x00000005
#define NUMAKER_CLK_LPTMRSEL_LPTMR1SEL_PCLK4 0x00000000
#define NUMAKER_CLK_LPTMRSEL_LPTMR1SEL_LXT 0x00000010
#define NUMAKER_CLK_LPTMRSEL_LPTMR1SEL_LIRC 0x00000020
#define NUMAKER_CLK_LPTMRSEL_LPTMR1SEL_MIRC 0x00000030
#define NUMAKER_CLK_LPTMRSEL_LPTMR1SEL_HIRC 0x00000040
#define NUMAKER_CLK_LPTMRSEL_LPTMR1SEL_EXT 0x00000050
#define NUMAKER_CLK_LPUARTSEL_LPUART0SEL_PCLK4 0x00000000
#define NUMAKER_CLK_LPUARTSEL_LPUART0SEL_LXT 0x00000001
#define NUMAKER_CLK_LPUARTSEL_LPUART0SEL_MIRC 0x00000002
#define NUMAKER_CLK_LPUARTSEL_LPUART0SEL_HIRC 0x00000003
#define NUMAKER_CLK_PSIOSEL_PSIO0SEL_LXT 0x00000000
#define NUMAKER_CLK_PSIOSEL_PSIO0SEL_HXT 0x00000001
#define NUMAKER_CLK_PSIOSEL_PSIO0SEL_LIRC 0x00000002
#define NUMAKER_CLK_PSIOSEL_PSIO0SEL_HIRC 0x00000003
#define NUMAKER_CLK_PSIOSEL_PSIO0SEL_HIRC48M_DIV4 0x00000004
#define NUMAKER_CLK_PSIOSEL_PSIO0SEL_PCLK1 0x00000005
#define NUMAKER_CLK_PSIOSEL_PSIO0SEL_APLL0_DIV2 0x00000006
#define NUMAKER_CLK_QSPISEL_QSPI0SEL_HXT 0x00000000
#define NUMAKER_CLK_QSPISEL_QSPI0SEL_APLL0_DIV2 0x00000001
#define NUMAKER_CLK_QSPISEL_QSPI0SEL_PCLK0 0x00000002
#define NUMAKER_CLK_QSPISEL_QSPI0SEL_HIRC 0x00000003
#define NUMAKER_CLK_QSPISEL_QSPI0SEL_HIRC48M_DIV4 0x00000004
#define NUMAKER_CLK_QSPISEL_QSPI1SEL_HXT 0x00000000
#define NUMAKER_CLK_QSPISEL_QSPI1SEL_APLL0_DIV2 0x00000010
#define NUMAKER_CLK_QSPISEL_QSPI1SEL_PCLK2 0x00000020
#define NUMAKER_CLK_QSPISEL_QSPI1SEL_HIRC 0x00000030
#define NUMAKER_CLK_QSPISEL_QSPI1SEL_HIRC48M_DIV4 0x00000040
#define NUMAKER_CLK_SCSEL_SC0SEL_HXT 0x00000000
#define NUMAKER_CLK_SCSEL_SC0SEL_APLL0_DIV2 0x00000001
#define NUMAKER_CLK_SCSEL_SC0SEL_PCLK1 0x00000002
#define NUMAKER_CLK_SCSEL_SC0SEL_HIRC 0x00000003
#define NUMAKER_CLK_SCSEL_SC0SEL_HIRC48M_DIV4 0x00000004
#define NUMAKER_CLK_SCSEL_SC1SEL_HXT 0x00000000
#define NUMAKER_CLK_SCSEL_SC1SEL_APLL0_DIV2 0x00000010
#define NUMAKER_CLK_SCSEL_SC1SEL_PCLK3 0x00000020
#define NUMAKER_CLK_SCSEL_SC1SEL_HIRC 0x00000030
#define NUMAKER_CLK_SCSEL_SC1SEL_HIRC48M_DIV4 0x00000040
#define NUMAKER_CLK_SCSEL_SC2SEL_HXT 0x00000000
#define NUMAKER_CLK_SCSEL_SC2SEL_APLL0_DIV2 0x00000100
#define NUMAKER_CLK_SCSEL_SC2SEL_PCLK1 0x00000200
#define NUMAKER_CLK_SCSEL_SC2SEL_HIRC 0x00000300
#define NUMAKER_CLK_SCSEL_SC2SEL_HIRC48M_DIV4 0x00000400
#define NUMAKER_CLK_SDHSEL_SDH0SEL_HXT 0x00000000
#define NUMAKER_CLK_SDHSEL_SDH0SEL_APLL1_DIV2 0x00000001
#define NUMAKER_CLK_SDHSEL_SDH0SEL_HCLK0 0x00000002
#define NUMAKER_CLK_SDHSEL_SDH0SEL_HIRC 0x00000003
#define NUMAKER_CLK_SDHSEL_SDH0SEL_HIRC48M_DIV4 0x00000004
#define NUMAKER_CLK_SDHSEL_SDH1SEL_HXT 0x00000000
#define NUMAKER_CLK_SDHSEL_SDH1SEL_APLL1_DIV2 0x00000010
#define NUMAKER_CLK_SDHSEL_SDH1SEL_HCLK0 0x00000020
#define NUMAKER_CLK_SDHSEL_SDH1SEL_HIRC 0x00000030
#define NUMAKER_CLK_SDHSEL_SDH1SEL_HIRC48M_DIV4 0x00000040
#define NUMAKER_CLK_SPISEL_SPI0SEL_HXT 0x00000000
#define NUMAKER_CLK_SPISEL_SPI0SEL_APLL1_DIV2 0x00000001
#define NUMAKER_CLK_SPISEL_SPI0SEL_APLL0_DIV2 0x00000002
#define NUMAKER_CLK_SPISEL_SPI0SEL_PCLK0 0x00000003
#define NUMAKER_CLK_SPISEL_SPI0SEL_HIRC 0x00000004
#define NUMAKER_CLK_SPISEL_SPI0SEL_HIRC48M 0x00000005
#define NUMAKER_CLK_SPISEL_SPI1SEL_HXT 0x00000000
#define NUMAKER_CLK_SPISEL_SPI1SEL_APLL1_DIV2 0x00000010
#define NUMAKER_CLK_SPISEL_SPI1SEL_APLL0_DIV2 0x00000020
#define NUMAKER_CLK_SPISEL_SPI1SEL_PCLK2 0x00000030
#define NUMAKER_CLK_SPISEL_SPI1SEL_HIRC 0x00000040
#define NUMAKER_CLK_SPISEL_SPI1SEL_HIRC48M 0x00000050
#define NUMAKER_CLK_SPISEL_SPI2SEL_HXT 0x00000000
#define NUMAKER_CLK_SPISEL_SPI2SEL_APLL1_DIV2 0x00000100
#define NUMAKER_CLK_SPISEL_SPI2SEL_APLL0_DIV2 0x00000200
#define NUMAKER_CLK_SPISEL_SPI2SEL_PCLK0 0x00000300
#define NUMAKER_CLK_SPISEL_SPI2SEL_HIRC 0x00000400
#define NUMAKER_CLK_SPISEL_SPI2SEL_HIRC48M 0x00000500
#define NUMAKER_CLK_SPISEL_SPI3SEL_HXT 0x00000000
#define NUMAKER_CLK_SPISEL_SPI3SEL_APLL1_DIV2 0x00001000
#define NUMAKER_CLK_SPISEL_SPI3SEL_APLL0_DIV2 0x00002000
#define NUMAKER_CLK_SPISEL_SPI3SEL_PCLK2 0x00003000
#define NUMAKER_CLK_SPISEL_SPI3SEL_HIRC 0x00004000
#define NUMAKER_CLK_SPISEL_SPI3SEL_HIRC48M 0x00005000
#define NUMAKER_CLK_STSEL_ST0SEL_HXT 0x00000000
#define NUMAKER_CLK_STSEL_ST0SEL_HXT_DIV2 0x00000001
#define NUMAKER_CLK_STSEL_ST0SEL_ACLK_DIV2 0x00000002
#define NUMAKER_CLK_STSEL_ST0SEL_HIRC_DIV2 0x00000003
#define NUMAKER_CLK_STSEL_ACLK 0x00000008
#define NUMAKER_CLK_TMRSEL_TMR0SEL_HXT 0x00000000
#define NUMAKER_CLK_TMRSEL_TMR0SEL_LXT 0x00000001
#define NUMAKER_CLK_TMRSEL_TMR0SEL_PCLK1 0x00000002
#define NUMAKER_CLK_TMRSEL_TMR0SEL_EXT 0x00000003
#define NUMAKER_CLK_TMRSEL_TMR0SEL_LIRC 0x00000004
#define NUMAKER_CLK_TMRSEL_TMR0SEL_HIRC 0x00000005
#define NUMAKER_CLK_TMRSEL_TMR0SEL_HIRC48M_DIV4 0x00000006
#define NUMAKER_CLK_TMRSEL_TMR1SEL_HXT 0x00000000
#define NUMAKER_CLK_TMRSEL_TMR1SEL_LXT 0x00000010
#define NUMAKER_CLK_TMRSEL_TMR1SEL_PCLK1 0x00000020
#define NUMAKER_CLK_TMRSEL_TMR1SEL_EXT 0x00000030
#define NUMAKER_CLK_TMRSEL_TMR1SEL_LIRC 0x00000040
#define NUMAKER_CLK_TMRSEL_TMR1SEL_HIRC 0x00000050
#define NUMAKER_CLK_TMRSEL_TMR1SEL_HIRC48M_DIV4 0x00000060
#define NUMAKER_CLK_TMRSEL_TMR2SEL_HXT 0x00000000
#define NUMAKER_CLK_TMRSEL_TMR2SEL_LXT 0x00000100
#define NUMAKER_CLK_TMRSEL_TMR2SEL_PCLK3 0x00000200
#define NUMAKER_CLK_TMRSEL_TMR2SEL_EXT 0x00000300
#define NUMAKER_CLK_TMRSEL_TMR2SEL_LIRC 0x00000400
#define NUMAKER_CLK_TMRSEL_TMR2SEL_HIRC 0x00000500
#define NUMAKER_CLK_TMRSEL_TMR2SEL_HIRC48M_DIV4 0x00000600
#define NUMAKER_CLK_TMRSEL_TMR3SEL_HXT 0x00000000
#define NUMAKER_CLK_TMRSEL_TMR3SEL_LXT 0x00001000
#define NUMAKER_CLK_TMRSEL_TMR3SEL_PCLK3 0x00002000
#define NUMAKER_CLK_TMRSEL_TMR3SEL_EXT 0x00003000
#define NUMAKER_CLK_TMRSEL_TMR3SEL_LIRC 0x00004000
#define NUMAKER_CLK_TMRSEL_TMR3SEL_HIRC 0x00005000
#define NUMAKER_CLK_TMRSEL_TMR3SEL_HIRC48M_DIV4 0x00006000
#define NUMAKER_CLK_TTMRSEL_TTMR0SEL_PCLK4 0x00000000
#define NUMAKER_CLK_TTMRSEL_TTMR0SEL_LXT 0x00000001
#define NUMAKER_CLK_TTMRSEL_TTMR0SEL_LIRC 0x00000002
#define NUMAKER_CLK_TTMRSEL_TTMR0SEL_MIRC 0x00000003
#define NUMAKER_CLK_TTMRSEL_TTMR0SEL_HIRC 0x00000004
#define NUMAKER_CLK_TTMRSEL_TTMR1SEL_PCLK4 0x00000000
#define NUMAKER_CLK_TTMRSEL_TTMR1SEL_LXT 0x00000010
#define NUMAKER_CLK_TTMRSEL_TTMR1SEL_LIRC 0x00000020
#define NUMAKER_CLK_TTMRSEL_TTMR1SEL_MIRC 0x00000030
#define NUMAKER_CLK_TTMRSEL_TTMR1SEL_HIRC 0x00000040
#define NUMAKER_CLK_UARTSEL0_UART0SEL_HXT 0x00000000
#define NUMAKER_CLK_UARTSEL0_UART0SEL_HIRC 0x00000001
#define NUMAKER_CLK_UARTSEL0_UART0SEL_LXT 0x00000002
#define NUMAKER_CLK_UARTSEL0_UART0SEL_APLL0_DIV2 0x00000003
#define NUMAKER_CLK_UARTSEL0_UART0SEL_HIRC48M 0x00000004
#define NUMAKER_CLK_UARTSEL0_UART1SEL_HXT 0x00000000
#define NUMAKER_CLK_UARTSEL0_UART1SEL_HIRC 0x00000010
#define NUMAKER_CLK_UARTSEL0_UART1SEL_LXT 0x00000020
#define NUMAKER_CLK_UARTSEL0_UART1SEL_APLL0_DIV2 0x00000030
#define NUMAKER_CLK_UARTSEL0_UART1SEL_HIRC48M 0x00000040
#define NUMAKER_CLK_UARTSEL0_UART2SEL_HXT 0x00000000
#define NUMAKER_CLK_UARTSEL0_UART2SEL_HIRC 0x00000100
#define NUMAKER_CLK_UARTSEL0_UART2SEL_LXT 0x00000200
#define NUMAKER_CLK_UARTSEL0_UART2SEL_APLL0_DIV2 0x00000300
#define NUMAKER_CLK_UARTSEL0_UART2SEL_HIRC48M 0x00000400
#define NUMAKER_CLK_UARTSEL0_UART3SEL_HXT 0x00000000
#define NUMAKER_CLK_UARTSEL0_UART3SEL_HIRC 0x00001000
#define NUMAKER_CLK_UARTSEL0_UART3SEL_LXT 0x00002000
#define NUMAKER_CLK_UARTSEL0_UART3SEL_APLL0_DIV2 0x00003000
#define NUMAKER_CLK_UARTSEL0_UART3SEL_HIRC48M 0x00004000
#define NUMAKER_CLK_UARTSEL0_UART4SEL_HXT 0x00000000
#define NUMAKER_CLK_UARTSEL0_UART4SEL_HIRC 0x00010000
#define NUMAKER_CLK_UARTSEL0_UART4SEL_LXT 0x00020000
#define NUMAKER_CLK_UARTSEL0_UART4SEL_APLL0_DIV2 0x00030000
#define NUMAKER_CLK_UARTSEL0_UART4SEL_HIRC48M 0x00040000
#define NUMAKER_CLK_UARTSEL0_UART5SEL_HXT 0x00000000
#define NUMAKER_CLK_UARTSEL0_UART5SEL_HIRC 0x00100000
#define NUMAKER_CLK_UARTSEL0_UART5SEL_LXT 0x00200000
#define NUMAKER_CLK_UARTSEL0_UART5SEL_APLL0_DIV2 0x00300000
#define NUMAKER_CLK_UARTSEL0_UART5SEL_HIRC48M 0x00400000
#define NUMAKER_CLK_UARTSEL0_UART6SEL_HXT 0x00000000
#define NUMAKER_CLK_UARTSEL0_UART6SEL_HIRC 0x01000000
#define NUMAKER_CLK_UARTSEL0_UART6SEL_LXT 0x02000000
#define NUMAKER_CLK_UARTSEL0_UART6SEL_APLL0_DIV2 0x03000000
#define NUMAKER_CLK_UARTSEL0_UART6SEL_HIRC48M 0x04000000
#define NUMAKER_CLK_UARTSEL0_UART7SEL_HXT 0x00000000
#define NUMAKER_CLK_UARTSEL0_UART7SEL_HIRC 0x10000000
#define NUMAKER_CLK_UARTSEL0_UART7SEL_LXT 0x20000000
#define NUMAKER_CLK_UARTSEL0_UART7SEL_APLL0_DIV2 0x30000000
#define NUMAKER_CLK_UARTSEL0_UART7SEL_HIRC48M 0x40000000
#define NUMAKER_CLK_UARTSEL1_UART8SEL_HXT 0x00000000
#define NUMAKER_CLK_UARTSEL1_UART8SEL_HIRC 0x00000001
#define NUMAKER_CLK_UARTSEL1_UART8SEL_LXT 0x00000002
#define NUMAKER_CLK_UARTSEL1_UART8SEL_APLL0_DIV2 0x00000003
#define NUMAKER_CLK_UARTSEL1_UART8SEL_HIRC48M 0x00000004
#define NUMAKER_CLK_UARTSEL1_UART9SEL_HXT 0x00000000
#define NUMAKER_CLK_UARTSEL1_UART9SEL_HIRC 0x00000010
#define NUMAKER_CLK_UARTSEL1_UART9SEL_LXT 0x00000020
#define NUMAKER_CLK_UARTSEL1_UART9SEL_APLL0_DIV2 0x00000030
#define NUMAKER_CLK_UARTSEL1_UART9SEL_HIRC48M 0x00000040
#define NUMAKER_CLK_USBSEL_USBSEL_HIRC48M 0x00000000
#define NUMAKER_CLK_USBSEL_USBSEL_APLL1_DIV2 0x00000001
#define NUMAKER_CLK_WDTSEL_WDT0SEL_LXT 0x00000000
#define NUMAKER_CLK_WDTSEL_WDT0SEL_LIRC 0x00000001
#define NUMAKER_CLK_WDTSEL_WDT1SEL_LXT 0x00000000
#define NUMAKER_CLK_WDTSEL_WDT1SEL_LIRC 0x00000010
#define NUMAKER_CLK_WWDTSEL_WWDT0SEL_LIRC 0x00000000
#define NUMAKER_CLK_WWDTSEL_WWDT0SEL_LXT 0x00000001
#define NUMAKER_CLK_WWDTSEL_WWDT1SEL_LIRC 0x00000000
#define NUMAKER_CLK_WWDTSEL_WWDT1SEL_LXT 0x00000010
#define NUMAKER_CLK_SCLKDIV_SCLKDIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_HCLKDIV_HCLK2DIV(x) (((x) - 1UL) << (8))
#define NUMAKER_CLK_PCLKDIV_PCLK0DIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_PCLKDIV_PCLK1DIV(x) (((x) - 1UL) << (4))
#define NUMAKER_CLK_PCLKDIV_PCLK2DIV(x) (((x) - 1UL) << (8))
#define NUMAKER_CLK_PCLKDIV_PCLK3DIV(x) (((x) - 1UL) << (12))
#define NUMAKER_CLK_PCLKDIV_PCLK4DIV(x) (((x) - 1UL) << (16))
#define NUMAKER_CLK_STDIV_ST0DIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_CANFDDIV_CANFD0DIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_CANFDDIV_CANFD1DIV(x) (((x) - 1UL) << (8))
#define NUMAKER_CLK_DMICDIV_DMIC0DIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_EADCDIV_EADC0DIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_I2SDIV_I2S0DIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_I2SDIV_I2S1DIV(x) (((x) - 1UL) << (8))
#define NUMAKER_CLK_KPIDIV_KPI0DIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_LPADCDIV_LPADC0DIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_LPUARTDIV_LPUART0DIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_PSIODIV_PSIO0DIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_SCDIV_SC0DIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_SCDIV_SC1DIV(x) (((x) - 1UL) << (8))
#define NUMAKER_CLK_SCDIV_SC2DIV(x) (((x) - 1UL) << (16))
#define NUMAKER_CLK_SDHDIV_SDH0DIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_SDHDIV_SDH1DIV(x) (((x) - 1UL) << (8))
#define NUMAKER_CLK_UARTDIV0_UART0DIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_UARTDIV0_UART1DIV(x) (((x) - 1UL) << (4))
#define NUMAKER_CLK_UARTDIV0_UART2DIV(x) (((x) - 1UL) << (8))
#define NUMAKER_CLK_UARTDIV0_UART3DIV(x) (((x) - 1UL) << (12))
#define NUMAKER_CLK_UARTDIV0_UART4DIV(x) (((x) - 1UL) << (16))
#define NUMAKER_CLK_UARTDIV0_UART5DIV(x) (((x) - 1UL) << (20))
#define NUMAKER_CLK_UARTDIV0_UART6DIV(x) (((x) - 1UL) << (24))
#define NUMAKER_CLK_UARTDIV0_UART7DIV(x) (((x) - 1UL) << (28))
#define NUMAKER_CLK_UARTDIV1_UART8DIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_UARTDIV1_UART9DIV(x) (((x) - 1UL) << (4))
#define NUMAKER_CLK_USBDIV_USBDIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_VSENSEDIV_VSENSEDIV(x) (((x) - 1UL) << (0))
#define NUMAKER_CLK_APLL0_SELECT 0x00000000
#define NUMAKER_CLK_APLL1_SELECT 0x00000001
#define NUMAKER_CLK_APLLCTL_APLLSRC_HXT 0x00000000
#define NUMAKER_CLK_APLLCTL_APLLSRC_HXT_DIV2 0x00000001
#define NUMAKER_CLK_APLLCTL_APLLSRC_HIRC 0x00000002
#define NUMAKER_CLK_APLLCTL_APLLSRC_HIRC48_DIV4 0x00000003
#define NUMAKER_ACMP01_MODULE 0
#define NUMAKER_ACMP23_MODULE 1
#define NUMAKER_AWF0_MODULE 2
#define NUMAKER_BPWM0_MODULE 3
#define NUMAKER_BPWM1_MODULE 4
#define NUMAKER_CANFD0_MODULE 5
#define NUMAKER_CANFD1_MODULE 6
#define NUMAKER_CCAP0_MODULE 7
#define NUMAKER_CRC0_MODULE 8
#define NUMAKER_CRYPTO0_MODULE 9
#define NUMAKER_DAC01_MODULE 10
#define NUMAKER_DMIC0_MODULE 11
#define NUMAKER_VAD0SEL_MODULE 12
#define NUMAKER_EADC0_MODULE 13
#define NUMAKER_EBI0_MODULE 14
#define NUMAKER_ECAP0_MODULE 15
#define NUMAKER_ECAP1_MODULE 16
#define NUMAKER_ECAP2_MODULE 17
#define NUMAKER_ECAP3_MODULE 18
#define NUMAKER_EMAC0_MODULE 19
#define NUMAKER_EPWM0_MODULE 20
#define NUMAKER_EPWM1_MODULE 21
#define NUMAKER_EQEI0_MODULE 22
#define NUMAKER_EQEI1_MODULE 23
#define NUMAKER_EQEI2_MODULE 24
#define NUMAKER_EQEI3_MODULE 25
#define NUMAKER_FMC0_MODULE 26
#define NUMAKER_ISP0_MODULE 27
#define NUMAKER_GDMA0_MODULE 28
#define NUMAKER_GPIOA_MODULE 29
#define NUMAKER_GPIOB_MODULE 30
#define NUMAKER_GPIOC_MODULE 31
#define NUMAKER_GPIOD_MODULE 32
#define NUMAKER_GPIOE_MODULE 33
#define NUMAKER_GPIOF_MODULE 34
#define NUMAKER_GPIOG_MODULE 35
#define NUMAKER_GPIOH_MODULE 36
#define NUMAKER_GPIOI_MODULE 37
#define NUMAKER_GPIOJ_MODULE 38
#define NUMAKER_HSOTG0_MODULE 39
#define NUMAKER_HSUSBD0_MODULE 40
#define NUMAKER_HSUSBH0_MODULE 41
#define NUMAKER_I2C0_MODULE 42
#define NUMAKER_I2C1_MODULE 43
#define NUMAKER_I2C2_MODULE 44
#define NUMAKER_I2C3_MODULE 45
#define NUMAKER_I2S0_MODULE 46
#define NUMAKER_I2S1_MODULE 47
#define NUMAKER_I3C0_MODULE 48
#define NUMAKER_KDF0_MODULE 49
#define NUMAKER_KPI0_MODULE 50
#define NUMAKER_KS0_MODULE 51
#define NUMAKER_LPADC0_MODULE 52
#define NUMAKER_LPPDMA0_MODULE 53
#define NUMAKER_LPGPIO0_MODULE 54
#define NUMAKER_LPI2C0_MODULE 55
#define NUMAKER_LPSPI0_MODULE 56
#define NUMAKER_LPSRAM0_MODULE 57
#define NUMAKER_LPTMR0_MODULE 58
#define NUMAKER_LPTMR1_MODULE 59
#define NUMAKER_LPUART0_MODULE 60
#define NUMAKER_NPU0_MODULE 61
#define NUMAKER_OTFC0_MODULE 62
#define NUMAKER_OTG0_MODULE 63
#define NUMAKER_PDMA0_MODULE 64
#define NUMAKER_PDMA1_MODULE 65
#define NUMAKER_PSIO0_MODULE 66
#define NUMAKER_QSPI0_MODULE 67
#define NUMAKER_QSPI1_MODULE 68
#define NUMAKER_RTC0_MODULE 69
#define NUMAKER_SC0_MODULE 70
#define NUMAKER_SC1_MODULE 71
#define NUMAKER_SC2_MODULE 72
#define NUMAKER_SCU0_MODULE 73
#define NUMAKER_SDH0_MODULE 74
#define NUMAKER_SDH1_MODULE 75
#define NUMAKER_SPI0_MODULE 76
#define NUMAKER_SPI1_MODULE 77
#define NUMAKER_SPI2_MODULE 78
#define NUMAKER_SPI3_MODULE 79
#define NUMAKER_SPIM0_MODULE 80
#define NUMAKER_SRAM0_MODULE 81
#define NUMAKER_SRAM1_MODULE 82
#define NUMAKER_SRAM2_MODULE 83
#define NUMAKER_SRAM3_MODULE 84
#define NUMAKER_ST0_MODULE 85
#define NUMAKER_TMR0_MODULE 86
#define NUMAKER_TMR1_MODULE 87
#define NUMAKER_TMR2_MODULE 88
#define NUMAKER_TMR3_MODULE 89
#define NUMAKER_TRNG0_MODULE 90
#define NUMAKER_TTMR0_MODULE 91
#define NUMAKER_TTMR1_MODULE 92
#define NUMAKER_UART0_MODULE 93
#define NUMAKER_UART1_MODULE 94
#define NUMAKER_UART2_MODULE 95
#define NUMAKER_UART3_MODULE 96
#define NUMAKER_UART4_MODULE 97
#define NUMAKER_UART5_MODULE 98
#define NUMAKER_UART6_MODULE 99
#define NUMAKER_UART7_MODULE 100
#define NUMAKER_UART8_MODULE 101
#define NUMAKER_UART9_MODULE 102
#define NUMAKER_USBD0_MODULE 103
#define NUMAKER_USBH0_MODULE 104
#define NUMAKER_USCI0_MODULE 105
#define NUMAKER_UTCPD0_MODULE 106
#define NUMAKER_WDT0_MODULE 107
#define NUMAKER_WDT1_MODULE 108
#define NUMAKER_WWDT0_MODULE 109
#define NUMAKER_WWDT1_MODULE 110
#define NUMAKER_PMC_NPD0 0x00000000
#define NUMAKER_PMC_NPD1 0x00000001
#define NUMAKER_PMC_NPD2 0x00000002
#define NUMAKER_PMC_NPD3 0x00000003
#define NUMAKER_PMC_NPD4 0x00000004
#define NUMAKER_PMC_SPD0 0x00000005
#define NUMAKER_PMC_SPD1 0x00000006
#define NUMAKER_PMC_DPD 0x00000007
#endif

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include/zephyr/dt-bindings/reset/numaker_m55m1x_reset.h Normal file
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/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M55M1X_RESET_H
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M55M1X_RESET_H
/* Beginning of M55M1 BSP sys_reg.h reset module copy */
#define SYS_RSTCTL_CHIPRST_Pos 0
#define SYS_RSTCTL_NPURST_Pos 6
#define SYS_ACMPRST_ACMP01RST_Pos 0
#define SYS_ACMPRST_ACMP23RST_Pos 1
#define SYS_AWFRST_AWF0RST_Pos 0
#define SYS_BPWMRST_BPWM0RST_Pos 0
#define SYS_BPWMRST_BPWM1RST_Pos 1
#define SYS_CANFDRST_CANFD0RST_Pos 0
#define SYS_CANFDRST_CANFD1RST_Pos 1
#define SYS_CCAPRST_CCAP0RST_Pos 0
#define SYS_CRCRST_CRC0RST_Pos 0
#define SYS_CRYPTORST_CRYPTO0RST_Pos 0
#define SYS_DACRST_DAC01RST_Pos 0
#define SYS_DMICRST_DMIC0RST_Pos 0
#define SYS_EADCRST_EADC0RST_Pos 0
#define SYS_EBIRST_EBI0RST_Pos 0
#define SYS_ECAPRST_ECAP0RST_Pos 0
#define SYS_ECAPRST_ECAP1RST_Pos 1
#define SYS_ECAPRST_ECAP2RST_Pos 2
#define SYS_ECAPRST_ECAP3RST_Pos 3
#define SYS_EMACRST_EMAC0RST_Pos 0
#define SYS_EPWMRST_EPWM0RST_Pos 0
#define SYS_EPWMRST_EPWM1RST_Pos 1
#define SYS_EQEIRST_EQEI0RST_Pos 0
#define SYS_EQEIRST_EQEI1RST_Pos 1
#define SYS_EQEIRST_EQEI2RST_Pos 2
#define SYS_EQEIRST_EQEI3RST_Pos 3
#define SYS_FMCRST_FMC0RST_Pos 0
#define SYS_GDMARST_GDMA0RST_Pos 0
#define SYS_GPIORST_GPIO0RST_Pos 0
#define SYS_HSOTGRST_HSOTG0RST_Pos 0
#define SYS_HSUSBDRST_HSUSBD0RST_Pos 0
#define SYS_HSUSBHRST_HSUSBH0RST_Pos 0
#define SYS_I2CRST_I2C0RST_Pos 0
#define SYS_I2CRST_I2C1RST_Pos 1
#define SYS_I2CRST_I2C2RST_Pos 2
#define SYS_I2CRST_I2C3RST_Pos 3
#define SYS_I2SRST_I2S0RST_Pos 0
#define SYS_I2SRST_I2S1RST_Pos 1
#define SYS_I3CRST_I3C0RST_Pos 0
#define SYS_KDFRST_KDF0RST_Pos 0
#define SYS_KPIRST_KPI0RST_Pos 0
#define SYS_KSRST_KS0RST_Pos 0
#define SYS_LPADCRST_LPADC0RST_Pos 0
#define SYS_LPPDMARST_LPPDMA0RST_Pos 0
#define SYS_LPGPIORST_LPGPIO0RST_Pos 0
#define SYS_LPI2CRST_LPI2C0RST_Pos 0
#define SYS_LPSPIRST_LPSPI0RST_Pos 0
#define SYS_LPTMRRST_LPTMR0RST_Pos 0
#define SYS_LPTMRRST_LPTMR1RST_Pos 1
#define SYS_LPUARTRST_LPUART0RST_Pos 0
#define SYS_OTFCRST_OTFC0RST_Pos 0
#define SYS_OTGRST_OTG0RST_Pos 0
#define SYS_PDMARST_PDMA0RST_Pos 0
#define SYS_PDMARST_PDMA1RST_Pos 1
#define SYS_PSIORST_PSIO0RST_Pos 0
#define SYS_QSPIRST_QSPI0RST_Pos 0
#define SYS_QSPIRST_QSPI1RST_Pos 1
#define SYS_RTCRST_RTC0RST_Pos 0
#define SYS_SCRST_SC0RST_Pos 0
#define SYS_SCRST_SC1RST_Pos 1
#define SYS_SCRST_SC2RST_Pos 2
#define SYS_SCURST_SCU0RST_Pos 0
#define SYS_SDHRST_SDH0RST_Pos 0
#define SYS_SDHRST_SDH1RST_Pos 1
#define SYS_SPIRST_SPI0RST_Pos 0
#define SYS_SPIRST_SPI1RST_Pos 1
#define SYS_SPIRST_SPI2RST_Pos 2
#define SYS_SPIRST_SPI3RST_Pos 3
#define SYS_SPIMRST_SPIM0RST_Pos 0
#define SYS_TMRRST_TMR0RST_Pos 0
#define SYS_TMRRST_TMR1RST_Pos 1
#define SYS_TMRRST_TMR2RST_Pos 2
#define SYS_TMRRST_TMR3RST_Pos 3
#define SYS_TRNGRST_TRNG0RST_Pos 0
#define SYS_TTMRRST_TTMR0RST_Pos 0
#define SYS_TTMRRST_TTMR1RST_Pos 1
#define SYS_UARTRST_UART0RST_Pos 0
#define SYS_UARTRST_UART1RST_Pos 1
#define SYS_UARTRST_UART2RST_Pos 2
#define SYS_UARTRST_UART3RST_Pos 3
#define SYS_UARTRST_UART4RST_Pos 4
#define SYS_UARTRST_UART5RST_Pos 5
#define SYS_UARTRST_UART6RST_Pos 6
#define SYS_UARTRST_UART7RST_Pos 7
#define SYS_UARTRST_UART8RST_Pos 8
#define SYS_UARTRST_UART9RST_Pos 9
#define SYS_USBDRST_USBD0RST_Pos 0
#define SYS_USBHRST_USBH0RST_Pos 0
#define SYS_USCIRST_USCI0RST_Pos 0
#define SYS_UTCPDRST_UTCPD0RST_Pos 0
#define SYS_WWDTRST_WWDT0RST_Pos 0
#define SYS_WWDTRST_WWDT1RST_Pos 1
/* End of M55M1 BSP sys_reg.h reset module copy */
/* Beginning of M55M1 BSP sys.h reset module copy */
/*---------------------------------------------------------------------
* Module Reset Control Resister constant definitions.
*---------------------------------------------------------------------
*/
#define NUMAKER_SYS_ACMP01RST ((0x200UL<<20) | SYS_ACMPRST_ACMP01RST_Pos)
#define NUMAKER_SYS_ACMP23RST ((0x200UL<<20) | SYS_ACMPRST_ACMP23RST_Pos)
#define NUMAKER_SYS_AWF0RST ((0x204UL<<20) | SYS_AWFRST_AWF0RST_Pos)
#define NUMAKER_SYS_BPWM0RST ((0x208UL<<20) | SYS_BPWMRST_BPWM0RST_Pos)
#define NUMAKER_SYS_BPWM1RST ((0x208UL<<20) | SYS_BPWMRST_BPWM1RST_Pos)
#define NUMAKER_SYS_CANFD0RST ((0x20CUL<<20) | SYS_CANFDRST_CANFD0RST_Pos)
#define NUMAKER_SYS_CANFD1RST ((0x20CUL<<20) | SYS_CANFDRST_CANFD1RST_Pos)
#define NUMAKER_SYS_CCAP0RST ((0x210UL<<20) | SYS_CCAPRST_CCAP0RST_Pos)
#define NUMAKER_SYS_CRC0RST ((0x214UL<<20) | SYS_CRCRST_CRC0RST_Pos)
#define NUMAKER_SYS_CRYPTO0RST ((0x218UL<<20) | SYS_CRYPTORST_CRYPTO0RST_Pos)
#define NUMAKER_SYS_DAC01RST ((0x21CUL<<20) | SYS_DACRST_DAC01RST_Pos)
#define NUMAKER_SYS_DMIC0RST ((0x220UL<<20) | SYS_DMICRST_DMIC0RST_Pos)
#define NUMAKER_SYS_EADC0RST ((0x224UL<<20) | SYS_EADCRST_EADC0RST_Pos)
#define NUMAKER_SYS_EBI0RST ((0x228UL<<20) | SYS_EBIRST_EBI0RST_Pos)
#define NUMAKER_SYS_ECAP0RST ((0x22CUL<<20) | SYS_ECAPRST_ECAP0RST_Pos)
#define NUMAKER_SYS_ECAP1RST ((0x22CUL<<20) | SYS_ECAPRST_ECAP1RST_Pos)
#define NUMAKER_SYS_ECAP2RST ((0x22CUL<<20) | SYS_ECAPRST_ECAP2RST_Pos)
#define NUMAKER_SYS_ECAP3RST ((0x22CUL<<20) | SYS_ECAPRST_ECAP3RST_Pos)
#define NUMAKER_SYS_EMAC0RST ((0x230UL<<20) | SYS_EMACRST_EMAC0RST_Pos)
#define NUMAKER_SYS_EPWM0RST ((0x234UL<<20) | SYS_EPWMRST_EPWM0RST_Pos)
#define NUMAKER_SYS_EPWM1RST ((0x234UL<<20) | SYS_EPWMRST_EPWM1RST_Pos)
#define NUMAKER_SYS_EQEI0RST ((0x238UL<<20) | SYS_EQEIRST_EQEI0RST_Pos)
#define NUMAKER_SYS_EQEI1RST ((0x238UL<<20) | SYS_EQEIRST_EQEI1RST_Pos)
#define NUMAKER_SYS_EQEI2RST ((0x238UL<<20) | SYS_EQEIRST_EQEI2RST_Pos)
#define NUMAKER_SYS_EQEI3RST ((0x238UL<<20) | SYS_EQEIRST_EQEI3RST_Pos)
#define NUMAKER_SYS_FMC0RST ((0x23CUL<<20) | SYS_FMCRST_FMC0RST_Pos)
#define NUMAKER_SYS_GDMA0RST ((0x240UL<<20) | SYS_GDMARST_GDMA0RST_Pos)
#define NUMAKER_SYS_GPIO0RST ((0x244UL<<20) | SYS_GPIORST_GPIO0RST_Pos)
#define NUMAKER_SYS_HSOTG0RST ((0x248UL<<20) | SYS_HSOTGRST_HSOTG0RST_Pos)
#define NUMAKER_SYS_HSUSBD0RST ((0x24CUL<<20) | SYS_HSUSBDRST_HSUSBD0RST_Pos)
#define NUMAKER_SYS_HSUSBH0RST ((0x250UL<<20) | SYS_HSUSBHRST_HSUSBH0RST_Pos)
#define NUMAKER_SYS_I2C0RST ((0x254UL<<20) | SYS_I2CRST_I2C0RST_Pos)
#define NUMAKER_SYS_I2C1RST ((0x254UL<<20) | SYS_I2CRST_I2C1RST_Pos)
#define NUMAKER_SYS_I2C2RST ((0x254UL<<20) | SYS_I2CRST_I2C2RST_Pos)
#define NUMAKER_SYS_I2C3RST ((0x254UL<<20) | SYS_I2CRST_I2C3RST_Pos)
#define NUMAKER_SYS_I2S0RST ((0x258UL<<20) | SYS_I2SRST_I2S0RST_Pos)
#define NUMAKER_SYS_I2S1RST ((0x258UL<<20) | SYS_I2SRST_I2S1RST_Pos)
#define NUMAKER_SYS_I3C0RST ((0x25CUL<<20) | SYS_I3CRST_I3C0RST_Pos)
#define NUMAKER_SYS_KDF0RST ((0x260UL<<20) | SYS_KDFRST_KDF0RST_Pos)
#define NUMAKER_SYS_KPI0RST ((0x264UL<<20) | SYS_KPIRST_KPI0RST_Pos)
#define NUMAKER_SYS_KS0RST ((0x268UL<<20) | SYS_KSRST_KS0RST_Pos)
#define NUMAKER_SYS_LPADC0RST ((0x26CUL<<20) | SYS_LPADCRST_LPADC0RST_Pos)
#define NUMAKER_SYS_LPPDMA0RST ((0x270UL<<20) | SYS_LPPDMARST_LPPDMA0RST_Pos)
#define NUMAKER_SYS_LPGPIO0RST ((0x274UL<<20) | SYS_LPGPIORST_LPGPIO0RST_Pos)
#define NUMAKER_SYS_LPI2C0RST ((0x278UL<<20) | SYS_LPI2CRST_LPI2C0RST_Pos)
#define NUMAKER_SYS_LPSPI0RST ((0x27CUL<<20) | SYS_LPSPIRST_LPSPI0RST_Pos)
#define NUMAKER_SYS_LPTMR0RST ((0x280UL<<20) | SYS_LPTMRRST_LPTMR0RST_Pos)
#define NUMAKER_SYS_LPTMR1RST ((0x280UL<<20) | SYS_LPTMRRST_LPTMR1RST_Pos)
#define NUMAKER_SYS_LPUART0RST ((0x284UL<<20) | SYS_LPUARTRST_LPUART0RST_Pos)
#define NUMAKER_SYS_NPURST ((0x004UL<<20) | SYS_RSTCTL_NPURST_Pos)
#define NUMAKER_SYS_OTFC0RST ((0x288UL<<20) | SYS_OTFCRST_OTFC0RST_Pos)
#define NUMAKER_SYS_OTG0RST ((0x28CUL<<20) | SYS_OTGRST_OTG0RST_Pos)
#define NUMAKER_SYS_PDMA0RST ((0x290UL<<20) | SYS_PDMARST_PDMA0RST_Pos)
#define NUMAKER_SYS_PDMA1RST ((0x290UL<<20) | SYS_PDMARST_PDMA1RST_Pos)
#define NUMAKER_SYS_PSIO0RST ((0x294UL<<20) | SYS_PSIORST_PSIO0RST_Pos)
#define NUMAKER_SYS_QSPI0RST ((0x298UL<<20) | SYS_QSPIRST_QSPI0RST_Pos)
#define NUMAKER_SYS_QSPI1RST ((0x298UL<<20) | SYS_QSPIRST_QSPI1RST_Pos)
#define NUMAKER_SYS_RTC0RST ((0x29CUL<<20) | SYS_RTCRST_RTC0RST_Pos)
#define NUMAKER_SYS_SC0RST ((0x2A0UL<<20) | SYS_SCRST_SC0RST_Pos)
#define NUMAKER_SYS_SC1RST ((0x2A0UL<<20) | SYS_SCRST_SC1RST_Pos)
#define NUMAKER_SYS_SC2RST ((0x2A0UL<<20) | SYS_SCRST_SC2RST_Pos)
#define NUMAKER_SYS_SCU0RST ((0x2A4UL<<20) | SYS_SCURST_SCU0RST_Pos)
#define NUMAKER_SYS_SDH0RST ((0x2A8UL<<20) | SYS_SDHRST_SDH0RST_Pos)
#define NUMAKER_SYS_SDH1RST ((0x2A8UL<<20) | SYS_SDHRST_SDH1RST_Pos)
#define NUMAKER_SYS_SPI0RST ((0x2ACUL<<20) | SYS_SPIRST_SPI0RST_Pos)
#define NUMAKER_SYS_SPI1RST ((0x2ACUL<<20) | SYS_SPIRST_SPI1RST_Pos)
#define NUMAKER_SYS_SPI2RST ((0x2ACUL<<20) | SYS_SPIRST_SPI2RST_Pos)
#define NUMAKER_SYS_SPI3RST ((0x2ACUL<<20) | SYS_SPIRST_SPI3RST_Pos)
#define NUMAKER_SYS_SPIM0RST ((0x2B0UL<<20) | SYS_SPIMRST_SPIM0RST_Pos)
#define NUMAKER_SYS_TMR0RST ((0x2C0UL<<20) | SYS_TMRRST_TMR0RST_Pos)
#define NUMAKER_SYS_TMR1RST ((0x2C0UL<<20) | SYS_TMRRST_TMR1RST_Pos)
#define NUMAKER_SYS_TMR2RST ((0x2C0UL<<20) | SYS_TMRRST_TMR2RST_Pos)
#define NUMAKER_SYS_TMR3RST ((0x2C0UL<<20) | SYS_TMRRST_TMR3RST_Pos)
#define NUMAKER_SYS_TRNG0RST ((0x2C4UL<<20) | SYS_TRNGRST_TRNG0RST_Pos)
#define NUMAKER_SYS_TTMR0RST ((0x2C8UL<<20) | SYS_TTMRRST_TTMR0RST_Pos)
#define NUMAKER_SYS_TTMR1RST ((0x2C8UL<<20) | SYS_TTMRRST_TTMR1RST_Pos)
#define NUMAKER_SYS_UART0RST ((0x2CCUL<<20) | SYS_UARTRST_UART0RST_Pos)
#define NUMAKER_SYS_UART1RST ((0x2CCUL<<20) | SYS_UARTRST_UART1RST_Pos)
#define NUMAKER_SYS_UART2RST ((0x2CCUL<<20) | SYS_UARTRST_UART2RST_Pos)
#define NUMAKER_SYS_UART3RST ((0x2CCUL<<20) | SYS_UARTRST_UART3RST_Pos)
#define NUMAKER_SYS_UART4RST ((0x2CCUL<<20) | SYS_UARTRST_UART4RST_Pos)
#define NUMAKER_SYS_UART5RST ((0x2CCUL<<20) | SYS_UARTRST_UART5RST_Pos)
#define NUMAKER_SYS_UART6RST ((0x2CCUL<<20) | SYS_UARTRST_UART6RST_Pos)
#define NUMAKER_SYS_UART7RST ((0x2CCUL<<20) | SYS_UARTRST_UART7RST_Pos)
#define NUMAKER_SYS_UART8RST ((0x2CCUL<<20) | SYS_UARTRST_UART8RST_Pos)
#define NUMAKER_SYS_UART9RST ((0x2CCUL<<20) | SYS_UARTRST_UART9RST_Pos)
#define NUMAKER_SYS_USBD0RST ((0x2D0UL<<20) | SYS_USBDRST_USBD0RST_Pos)
#define NUMAKER_SYS_USBH0RST ((0x2D4UL<<20) | SYS_USBHRST_USBH0RST_Pos)
#define NUMAKER_SYS_USCI0RST ((0x2D8UL<<20) | SYS_USCIRST_USCI0RST_Pos)
#define NUMAKER_SYS_UTCPD0RST ((0x2DCUL<<20) | SYS_UTCPDRST_UTCPD0RST_Pos)
#define NUMAKER_SYS_WWDT0RST ((0x2E0UL<<20) | SYS_WWDTRST_WWDT0RST_Pos)
#define NUMAKER_SYS_WWDT1RST ((0x2E0UL<<20) | SYS_WWDTRST_WWDT1RST_Pos)
/* End of M55M1 BSP sys.h reset module copy */
#endif

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# Copyright (c) 2025 Nuvoton Technology Corporation.
#
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(soc.c)
zephyr_include_directories(.)
zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
zephyr_sources_ifdef(CONFIG_ARM_MPU mpu_regions.c)
zephyr_linker_sources(SECTIONS sections.ld)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

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soc/nuvoton/numaker/m55m1x/Kconfig Normal file
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# Copyright (c) 2025 Nuvoton Technology Corporation.
#
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_M55M1X
select ARM
select CPU_CORTEX_M55
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select ARMV8_M_DSP
select CPU_CORTEX_M_HAS_DWT
select ARMV8_1_M_PMU
select SOC_EARLY_INIT_HOOK
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
select HAS_POWEROFF
config ARMV8_1_M_PMU_EVENTCNT
int
default 8 if SOC_SERIES_M55M1X
config SOC_M55M1XXX
select HAS_NUMAKER_HAL

9
soc/nuvoton/numaker/m55m1x/Kconfig.defconfig Normal file
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# Copyright (c) 2025 Nuvoton Technology Corporation.
#
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_M55M1X
rsource "Kconfig.defconfig.m55m1*"
endif # SOC_SERIES_M55M1X

10
soc/nuvoton/numaker/m55m1x/Kconfig.defconfig.m55m1xxx Normal file
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# Copyright (c) 2025 Nuvoton Technology Corporation.
#
# SPDX-License-Identifier: Apache-2.0
if SOC_M55M1XXX
config NUM_IRQS
default 161
endif # SOC_M55M1XXX

19
soc/nuvoton/numaker/m55m1x/Kconfig.soc Normal file
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# Copyright (c) 2025 Nuvoton Technology Corporation.
#
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_M55M1X
bool
select SOC_FAMILY_NUMAKER
help
Enable support for Nuvoton M55M1X MCU series
config SOC_M55M1XXX
bool
select SOC_SERIES_M55M1X
config SOC_SERIES
default "m55m1x" if SOC_SERIES_M55M1X
config SOC
default "m55m1xxx" if SOC_M55M1XXX

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soc/nuvoton/numaker/m55m1x/mpu_regions.c Normal file
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/*
* Copyright (c) 2021 The Chromium OS Authors
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
static const struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("FLASH",
CONFIG_FLASH_BASE_ADDRESS,
REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, CONFIG_FLASH_SIZE * 1024)),
MPU_REGION_ENTRY("SRAM",
CONFIG_SRAM_BASE_ADDRESS,
REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, CONFIG_SRAM_SIZE * 1024)),
#if DT_NODE_EXISTS(DT_NODELABEL(itcm))
MPU_REGION_ENTRY("ITCM",
DT_REG_ADDR(DT_NODELABEL(itcm)),
REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(itcm)),
DT_REG_SIZE(DT_NODELABEL(itcm)))),
#endif
#if DT_NODE_EXISTS(DT_NODELABEL(dtcm))
MPU_REGION_ENTRY("DTCM",
DT_REG_ADDR(DT_NODELABEL(dtcm)),
REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(dtcm)),
DT_REG_SIZE(DT_NODELABEL(dtcm)))),
#endif
};
const struct arm_mpu_config mpu_config = {
.num_regions = ARRAY_SIZE(mpu_regions),
.mpu_regions = mpu_regions,
};

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soc/nuvoton/numaker/m55m1x/poweroff.c Normal file
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/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
#include <zephyr/sys/poweroff.h>
#include <NuMicro.h>
void z_sys_poweroff(void)
{
SYS_UnlockReg();
/* Select Power-down mode */
PMC_SetPowerDownMode(DT_PROP_OR(DT_NODELABEL(scc), powerdown_mode, PMC_SPD0),
PMC_PLCTL_PLSEL_PL0);
/* Clear all wake-up flag */
PMC->INTSTS |= PMC_INTSTS_CLRWK_Msk;
/* Enter to Power-down mode */
PMC_PowerDown();
k_cpu_idle();
CODE_UNREACHABLE;
}

18
soc/nuvoton/numaker/m55m1x/sections.ld Normal file
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/*
* Copyright (c) 2020 Mario Jaun
*
* SPDX-License-Identifier: Apache-2.0
*/
#if DT_NODE_EXISTS(DT_NODELABEL(dtcm))
.dtcm_noinit (NOLOAD) : SUBALIGN(4)
{
__dtcm_noinit_start = .;
*(.dtcm_noinit)
*(".dtcm_noinit.*")
*(".kernel_noinit.*")
*(".noinit.*kernel/init.*")
*(".noinit.*kernel/mempool.*")
__dtcm_noinit_end = .;
} > DTCM
#endif

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/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
#include <zephyr/cache.h>
#include <zephyr/drivers/clock_control/clock_control_numaker.h>
/* Hardware and starter kit includes. */
#include <NuMicro.h>
static void memory_setup(void)
{
/* Enable SRAM1/2 functions are only available in secure mode. */
if (SCU_IS_CPU_NS(SCU_NS) == 0) {
uint32_t wait_cnt;
/* To assign __HIRC value directly before BSS initialization. */
SystemCoreClock = __HIRC;
wait_cnt = SystemCoreClock;
/* Unlock protected registers */
do {
SYS->REGLCTL = 0x59UL;
SYS->REGLCTL = 0x16UL;
SYS->REGLCTL = 0x88UL;
} while (SYS->REGLCTL == 0UL);
/* Switch SRAM1 to normal power mode */
if (PMC->SYSRB1PC != 0) {
PMC->SYSRB1PC = 0;
}
/* Switch SRAM2 to normal power mode */
if (PMC->SYSRB2PC != 0) {
PMC->SYSRB2PC = 0;
}
/* Wait SRAM1/2 power mode change finish */
while (1) {
if ((PMC->SYSRB1PC & PMC_SYSRB1PC_PCBUSY_Msk) == 0 &&
(PMC->SYSRB2PC & PMC_SYSRB2PC_PCBUSY_Msk) == 0) {
break;
}
if (wait_cnt-- == 0) {
break;
}
}
/* Enable SRAM1/2 clock */
CLK->SRAMCTL |= (CLK_SRAMCTL_SRAM1CKEN_Msk | CLK_SRAMCTL_SRAM2CKEN_Msk);
}
#if (defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U))
/* Enable CP10 & CP11 Full Access */
SCB->CPACR |= ((3U << 10U * 2U) | (3U << 11U * 2U));
/* Set low-power state for PDEPU
* 0b00 | ON, PDEPU is not in low-power state
* 0b01 | ON, but the clock is off
* 0b10 | RET(ention)
* 0b11 | OFF
* Clear ELPSTATE, value is 0b11 on Cold reset
*/
PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk <<
PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos);
/* PDEPU ON with clock off, value is 0b01 */
PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
#endif
/* Enable only if configured to do so. */
SCB_InvalidateICache();
sys_cache_instr_enable();
/* Enable d-cache only if configured to do so. */
SCB_InvalidateDCache();
sys_cache_data_enable();
}
void soc_early_init_hook(void)
{
/* To ensure H/W I/O buffer with correct init data in SRAM,
* to clean D-Cache here to let all .bss & .data flush to SRAM.
*/
#ifdef CONFIG_DCACHE
SCB_CleanDCache();
#endif
SystemInit();
}
void soc_reset_hook(void)
{
memory_setup();
/* Unlock protected registers */
SYS_UnlockReg();
/* Release GPIO hold status */
PMC_RELEASE_GPIO();
/*
* -------------------
* Init System Clock
* -------------------
*/
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hxt)
/* Enable/disable 4~24 MHz external crystal oscillator (HXT) */
if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_ENABLE) {
CLK_EnableXtalRC(CLK_SRCCTL_HXTEN_Msk);
/* Wait for HXT clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
} else if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_DISABLE) {
CLK_DisableXtalRC(CLK_SRCCTL_HXTEN_Msk);
}
#endif
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), lxt)
/* Enable/disable 32.768 kHz low-speed external crystal oscillator (LXT) */
if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_ENABLE) {
CLK_EnableXtalRC(CLK_SRCCTL_LXTEN_Msk);
/* Wait for LXT clock ready */
CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
} else if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_DISABLE) {
CLK_DisableXtalRC(CLK_SRCCTL_LXTEN_Msk);
}
#endif
/* Enable 12 MHz high-speed internal RC oscillator (HIRC) */
CLK_EnableXtalRC(CLK_SRCCTL_HIRCEN_Msk);
/* Wait for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Enable 32 KHz low-speed internal RC oscillator (LIRC) */
CLK_EnableXtalRC(CLK_SRCCTL_LIRCEN_Msk);
/* Wait for LIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hirc48)
/* Enable/disable 48 MHz high-speed internal RC oscillator (HIRC48) */
if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_ENABLE) {
CLK_EnableXtalRC(CLK_SRCCTL_HIRC48MEN_Msk);
/* Wait for HIRC48 clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRC48MSTB_Msk);
} else if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_DISABLE) {
CLK_DisableXtalRC(CLK_SRCCTL_HIRC48MEN_Msk);
}
#endif
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), clk_pclkdiv)
/* Set CLK_PCLKDIV register on request */
CLK->PCLKDIV = DT_PROP(DT_NODELABEL(scc), clk_pclkdiv);
#endif
#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), core_clock)
/* Set core clock (HCLK) on request */
CLK_SetCoreClock(DT_PROP(DT_NODELABEL(scc), core_clock));
#endif
/*
* Update System Core Clock
* User can use SystemCoreClockUpdate() to calculate SystemCoreClock.
*/
SystemCoreClockUpdate();
/* Lock protected registers */
SYS_LockReg();
}

13
soc/nuvoton/numaker/m55m1x/soc.h Normal file
View file

@ -0,0 +1,13 @@
/*
* Copyright (c) 2025 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_ARM_NUVOTON_M55M1X_SOC_H_
#define ZEPHYR_SOC_ARM_NUVOTON_M55M1X_SOC_H_
/* Hardware and starter kit includes. */
#include <NuMicro.h>
#endif /* ZEPHYR_SOC_ARM_NUVOTON_M55M1X_SOC_H_*/

3
soc/nuvoton/numaker/soc.yml
View file

@ -7,3 +7,6 @@ family:
- name: m2l31x
socs:
- name: m2l31xxx
- name: m55m1x
socs:
- name: m55m1xxx