soc: xlnx: zynqmp: Enable I/D caches

On ZynqMP, the RPU Cortex-R5 cores come up by default without
instruction and data caches enabled. Enable them as part of
soc_early_init_hook when CONFIG_CACHE_MANAGEMENT is enabled.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>

soc/xlnx/zynqmp/Kconfig

@@ -6,5 +6,6 @@ config SOC_XILINX_ZYNQMP_RPU
 	select ARM
 	select CPU_CORTEX_R5
 	select SOC_RESET_HOOK
+	select SOC_EARLY_INIT_HOOK
 	select CPU_HAS_ARM_MPU
 	select VFP_DP_D16

soc/xlnx/zynqmp/soc.c

@@ -7,6 +7,7 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
+#include <zephyr/cache.h>
 
 #include <cmsis_core.h>
 
@@ -20,3 +21,10 @@ void soc_reset_hook(void)
 	sctlr &= ~SCTLR_V_Msk;
 	__set_SCTLR(sctlr);
 }
+
+void soc_early_init_hook(void)
+{
+	/* Enable caches */
+	sys_cache_instr_enable();
+	sys_cache_data_enable();
+}