Add clock initialization for MIPI and LCIDF to NXP RT5xx SOC.
Note that clock divider properties are used by both initialization
routines, as the required clock divider will vary depending on
attached display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This is a follow-up to commit 7195db01f4.
Restore the check that was accidentaliy removed in the above commit,
so that the message is again logged only once per detection of the
anomaly 160 conditions.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Now building twice back to back does not build anything the second time
when CONFIG_CLEANUP_INTERMEDIATE_FILES (which obviously breaks
incremental builds) is also turned off.
Fixes commit 2906d1aa51 ("soc/intel_adsp: Build bootloader with Zephyr")
Properly implementing custom commands requires BOTH
`add_custom_command()` and an `add_custom_target()` wrapper with some
careful DEPENDS wizardry between them.
https://cmake.org/cmake/help/latest/command/add_custom_target.html
> Use the add_custom_command() command to generate a file with
> dependencies.
The documentation of add_custom_command() also similarly refers to
add_custom_target()
When this is not done properly, the build is cursed in various, very
time-consuming ways which are not officially documented but here
instead:
https://samthursfield.wordpress.com/2015/11/21/cmake-dependencies-between-targets-and-files-and-custom-commands
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
This is a bugfix. It uses the right storage label `slot0_partition` for
esp32s2. Note that this is already the case for esp32 and esp32s3.
This should address
https://github.com/zephyrproject-rtos/zephyr/issues/55286.
Signed-off-by: Ning Shang <syncom.dev@gmail.com>
This is a follow-up to commit fe3b97a87f.
This message should not be a warning, as it does not actually indicate
that something potentially bad happened. On the contrary, it informs
that conditions in which the anomaly 160 could occur were detected and
the anomaly was prevented from occurring. There is no need for this
message to appear in the default configuration (INFO level). In fact,
the message would undesirably flood the console in some cases (like
the kernel/mem_protect/stack_random test) and sometimes it would also
require enlarging the stack of the idle thread (the function is called
underneath k_cpu_idle()). Therefore, the logging level of this message
is changed to DEBUG.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Voltage comparator driver submits notifications into system work queue,
this change will make driver to use dedicated work queue, and priority
of dedicated work queue are configurable as well.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Added initial version of Infineon CAT1 Pin controller driver.
Added initial version of binding file for Infineon CAT1 Pinctrl driver.
Added initial version of dt header for Infineon CAT1 pinctrl driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Since PINCTRL and pinctrl-0 is now required, there's no point in doing
extra validation at driver level. Modify the macro to just check that
sleep state is present when needed, since it was the only remaining
assertion that was not covered. Renamed the macro to make it more clear
what it does: NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Update ESP32-C3 architecture as IMC instead IMA.
Although not documented, ESP32-S3 supports CSR instructions.
It also needs to be enabled, otherwise build will fail.
Fixes#53555
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
For RISCV arch, enable FLASH_SIZE and FLASH_BASE_ADDRESS config.
To avoid duplicated work, remove flash config from RISCV soc.
Signed-off-by: Jonas Otto <jonas@jonasotto.com>
Drop the non existing option PINMUX_XEC, this has been removed in
d76f4f2c8a drivers: pinmux: mchp_xec: drop driver
And is currently causing build errors.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add the stm32U5 serie for the support of the STM32_BACKUP_SRAM
The PWR peripheral is enabled by the soc/arm/st_stm32/stm32u5/soc.c
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes the following warning:
cavstool.py:706: DeprecationWarning: There is no current event loop
asyncio.get_event_loop().run_until_complete(main())
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
This is a follow-up to commit fe3b97a87f.
Add a cmake warning issued when the workaround for the nRF5340 anomaly
160 cannot be applied because the application is configured with no
system clock.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Drop STM32 pinmux driver in favor of pinctrl. Some definitions located
in pinmux headers were used by the pinctrl driver, so they have been
moved there.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Cleanup core if booting from bootloader using RT5xx. This is required
because the call to SystemInit will push data to the stack, and the
bootloader may have configured stack limits or MPU settings. Either
would cause the core to fault if these settings are not first
cleaned up.
Perform this cleanup if the boot header is not present, as in this case
the application was likely kicked off via a bootloader.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow to include boot header for code linked into
not only FlexSPI controlled memory.
Fixes#53867
Signed-off-by: Mikhail Siomin <victorovich.01@mail.ru>
Implement a workaround for the nRF53 anomaly 160. This consist of
a set of writes to certain hardware registers that is done at boot
and a piece of code that is executed when the CPU is made idle and
that prevents the CPU from switching between active and sleep modes
more than five times within a 200 us period.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use CMSIS SystemInit for all NXP iMX.RT SOCs, to simplify initialization
flow, and remove redundant code where possible.
Introduce Kconfigs to disable Cache at boot, since SystemInit will enable
code cache on these platforms, which may be undesirable behavior.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Convert NXP LPC SOCs to use CMSIS SystemInit, and remove redundant code
where it exists. This will enable initialization flows to be more
standardized across all platforms.
Since LPC54xxx and LPC55xxx series enables SRAM banks in SystemInit,
provide Kconfigs to bypass this setting and keep additional SRAM
banks unclocked.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add call to SystemInit for all NXP Kinetis SOCs and remove any
redundant code from initialization flow. This allows watchdog
initialization to be removed from all Kinetis SOCs as it is handled
by SystemInit.
Since Kinetis watchdog is enabled by default at boot, allow watchdog
setup to by bypassed with CONFIG_WDOG_ENABLE_AT_BOOT. This
setting requires the user to provide a watchdog configuration hook
using z_arm_watchdog_init, but will allow the watchdog to remain
enabled.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
update the endpint in dts to 6 to alignd with RM
enable usb-device for LPC55S28
all USB supported tests/samples PASS
samples:
scripts/twister -p lpcxpresso55s28 \
--device-testing --hardware-map ~/map.yml \
-T samples/subsys/usb/
...
INFO - 7 of 25 test configurations passed (100.00%),\
0 failed, 18 skipped with 0 warnings in 73.49 seconds
...
tests
scripts/twister -p lpcxpresso55s28 \
--device-testing --hardware-map ~/map.yml \
-T tests/subsys/usb/
...
INFO - 3 of 4 test configurations passed (100.00%),\
0 failed, 1 skipped with 0 warnings in 36.39 seconds
...
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Allow the the SoC to enter deep sleep when CONFIG_PM_DEVICE
is enabled. This will allow to selectively add low power
support for certain drivers like UART and ADC.
The previous checking of ifndef CONFIG_PM_DEVICE was
incorrect. The MEC172x requires the soc power file to perform
some operations when CONFIG_PM_DEVICE is enabled to allow
the hardware to shut down the PLL.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The watchdog is controlled by ll-scheduler and should not be resumed when
a core is bringing up. Watchdog pause control code was removed.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Added intel_adsp_ipc_send_message_emergency function that allows to send an
ipc message notifying about emergency event, such as watchdog timeout.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The non-maskable interrupt have no corresponding bit in INTERRUPT and
INTENABLE registers so its occurrence cannot be confirmed. Removed the code
that checked if the interrupt flag is set.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
rodata section for xtensa overrides the .ctors section
containing the constructor info and the _ZEPHYR_CTOR_LIST_.
Removes the ctor related linker script lines from the rodata
section of the ace linker script to ensure that the .ctors is
properly generated and placed when using the xcc-clang compiler.
Fixes#54730
Signed-off-by: Aastha Grover <aastha.grover@intel.com>
PR #30403 implemented nocache regions for ethernet DMA buffers in sram3 to
fix issue #29915. Unfortunately, some STM32H7 variants do not have any
sram3 so they still suffer from #29915.
All H7 variants have sram2 though, so use that for targets without sram3.
Signed-off-by: Björn Stenberg <bjorn@haxx.se>
When running the blinky example on STM32H747, with the BOOT_CM4 bit set
to 0, the M4 core goes into panic.
Increasing the value of the hardware semaphore retry prevents this.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This patch allows successive reflashing operation on stm32f3
boards by Enabling the Debug Module during SLEEP mode.
This will especially makes reflahing and debugging possible
with pyocd runner on west commands.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Temporary re-enabling interrupts before going to waiti. Right now
secondary cores don't have proper context restore flow and after leaving
D3 state core will return here and stuck. This is temporary workaround.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
