* Move definition of flexspi_nor_config_t into soc/ dir so it can
be shared by all i.MX RT based boards.
* Use Kconfig symbol CONFIG_NXP_IMX_RT_BOOT_HEADER instead of
HAL define (which is set based on the Kconfig symbol)
* Rename board files to flexspi_nor_config.c since they
are already namespaced by the board dir.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Introduce soc_port common functions. The sam0 pinmux driver was
refactored to use soc_port_pinmux_set common function.
This create the common base to implement sam0 pinctrl functions.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Some STM32 series (l0, g0, f0) needs to enable clock of
DBGMCU peripheral, before accessing registers
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Create a shared macro to access the pinctrl_0 property. The pinctrl_0
property includes pinmux phandle, pin and alternate function.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Move the implementation of z_platform_init from the NXP Hal
into the main Zephyr tree. This function is Zephyr-specific,
is part of the Zephyr module glue code, and does not need to
reside in the module repository. We also rename the function
to z_arm_platform_init. The commit does not introduce any
behavioral changes.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Platform specific initialization during early boot
has been a feature supported only by Cortex-M; the
Kconfig symbol is defined in arch/arm Kconfig space.
We rename the z_platform_init() function to
z_arm_platform_init(), to indicate more clearly that
this is an internal, private ARM-only API.
This commit does not introduce behavioral changes.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Create version 2 of the MEC GPIO driver to support MEC172x to not
interfere with MEC152x. When the MEC172x ECIA interrupt aggregator
driver is ready, this driver will use ECIA for registering GPIO
interrupt callbacks instead of maintaining its own interrupt table.
Add V2 DT binding.
Add the Kconfig configuration settings for the MEC172x GPIO
V2 driver at the SoC and board level.
Add port id to DT allowing use of DT FOR EACH macro in the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Update Microchip XEC RTOS timer driver adding MEC172x support and
using more device tree properities in the driver. We must also update
the XEC counter driver to use the new GIRQ DT properties.
Add new properties to RTOS timer and RTC timer YAML. These two timers
are linked due to option using a high speed timer for kernel busy wait.
Add Kconfig logic for XEC RTOS timer to MEC172x SoC.
Enable the Microchip XEC RTOS timer in the MEC172x evaluation board.
Add device tree nodes for most peripeherals.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
In commit "pm: Fix weak linkage symbols" (PR #35274),
PM SoC hooks were converted to __weak to avoid clash with
new definition of these symbols in subsys/pm/power.c.
In this process, few SoCs were missed.
Fix this.
#37226
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The KBC/ACPI event data is 4-byte in width and composed of
event/data/type fields. However, the field position is defined by each
chip vendor via macro and not unified in the current implementation.
The commit uses the structure bit field to define and unify the field
position. It helps the application access it with a common approach.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
it8xxx2 supports 'm', 'a', and 'c' extensions.
Enable them to save flash space and also improve
latency of fetching code from flash.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This CL replaces offset macros of pmc 'multi-registers' such as
PWDWN_CTLn with internal inline functions for better readability.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL replaces offset macros of scfg 'multi-registers' such as DEVALTn
and LV_GPIO_CTLn with internal inline functions for better readability.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add driver implementation and header files for a MEC172x
aggregated interrupt driver. Enable the parent(ECIA) node
to have the driver initialize interrupt hardware for use.
Enable child nodes for those GIRQs used for aggregation.
Refer to chip documention for the list of GIRQs restricted
to aggregation and those which support direct mode.
Add chip level device tree node for MEC172x EC interrupt
aggregator parent and GIRQ children. Each child node contains
a list of sources representing the source bit position in the
GIRQ registers.
Add DT bindings for ECIA and GIRQ nodes.
Add build file(s) and configuration items for the MEC172x ECIA
aggregated interrupt driver. Add and enable the MEC172x interrupt
driver on the MEC172x evaluation board(EVB). Enable parent node to
initialize ECIA hardware. Child nodes are left disabled until a
future driver needs them.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Define SoC hooks as weak symbols so this way applications can
overwritten them defining strong symbols.
The problem is that currently SoCs are defining these interfaces as
strong symbol inhibiting the possibility of applications bring their
own implementation.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Correct SYS_CLOCK_HW_CYCLES_PER_SEC and
SYS_CLOCK_TICKS_PER_SEC to match our real setting value
for precise timing.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Add the missing includes to make the header more portable. It currently
requires other headers to be included before it.
Signed-off-by: Yuval Peress <peress@chromium.org>
XCC's linker cannot properly process our linker script with
regard to cached/uncached memory regions as the linker cannot
correctly calculate addresses using boolean operations.
Fix this by doing address pointer arithmetic manually to
move between cached and uncached memory regions.
The addresses of symbols were compared via nm and they are
the same before and after this change.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
XCC's own xt-objcopy does not recognize the "--dump-section"
command. So simply copy the objecy file into binary so it can
be included in the final bootloader binary.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves the inclusion of sys/util.h inside the #if block to
avoid this being included when going through XCC's assembler.
With the old behavior, a bunch of std*.h get pulled in resulted
in build failure as keywords such as "typedef" are not supposed
to be in assembly files according to XCC assembler.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Implement a clock control driver for Microchip MEC172x handling
configuring the 32 KHz input sources for the PLL and peripheral-32k
clock domains. MEC172x differs from MEC152x. MEC152x had one 32K source
for both PLL and peripherals. MEC172x allows the two domains to use
independent 32 KHz sources. Device tree updated to provide addresses
of hardware used by the driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
cc13x2_cc26x2 had its own power policy that was implementing the same
logic available in the default residency policy. Also, this policy was
unnecessarily setting up a timeout to wakeup the system. This is not
necessary, the power subsystem takes care of this.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Implementation of hardware semaphore algorithm of STM32 AN5289
to enter and exit low power
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Add MEC172x chip specific headers for Port 80h debug
capture, quad SPI, and VBAT registers. Update due to
merges.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
reuse the lpc's lpadc driver for rt1170, modify the dts and add
some macro to shield some code of LPC series. Also add the
board support inside the tests/drivers/adc/adc_api/src/test_adc.c,
and a dts node:zephyr,user inside
samples/drivers/adc/boards/mimxrt1170_evk_cm7.overlay
Signed-off-by: Crist Xu <crist.xu@nxp.com>
Add Microchip MEC172x header set 5 chip specific
peripheral headers. Update with recent merged code.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Consensus was reached to locate Microchip MEC172x header files
in the zephyr MEC172x SoC folders. These are the first set of
headers specific to MEC172x and common to the MEC family. Hardware
register structures will be located in peripheral specific headers.
Update based on latest merge of MEC172x related files.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Adding support for the stm32l051 devices.
Signed-off-by: Even Falch-Larsen <even.falch.larsen@nomono.co>
Co-authored-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Added minimal device tree and board files to build Microchip
MEC172x. SOC layer stripped down to allow build for checking
compilation only.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Pin PB5 is part of ARM Cortex-M debug interface and by default
configured to output TDO/TRACESWO signal. Disable TDO/TRACESWO
function on PB5 pin when LOG_BACKEND_SWO is not enabled. This
ultimately frees the pin to be used by standard SoC peripherals.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit includes the following:
1. Add symbol for choice option. So we can override the default value
by an earlier definition.
2. NPCX9 doesn't support 33MHz SPI clock in the header. So disable the
option for NPCX9.
3. NPCX9 support 512K flash. Change default to 512k for NPCX9.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
To be able to get a tokenize DT string without the quotes. Deprecate
also DT_ENUM_TOKEN and DT_ENUM_UPPER_TOKEN.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Default Voltage scaling range selection (range2)
doesn't allow to configure Max frequency
switch to range1 to match any frequency
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Default Voltage scaling range selection (range2)
doesn't allow to configure Max frequency
switch to range1 to match any frequency
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
