Add OpenISA RV32M1 pinctrl header file to define SoC specific pinctrl_soc_t
structure. This is used to store pin configurations for the pinctrl driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This reverts commit 91d4b7766c.
Zephyr SDK 0.14.1 now includes QEMU 6.2, which supports the emulation
of the MVE instructions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Adds a log backend that maintains a ringbuffer in coordination
with cAVS HDA.
The DMA channel is expected to be given some time after the logger
starts so a seperate step to initialize the dma channel is required.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Update the Microchip XEC PS2 driver to support MEC172x.
NOTE: MEC15xx has two PS2 controllers and
MEC172x has one.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
add pincontrol headers for IOCON peripheral present on NXP iMX RT600
and RT500 SOCs, and update LPC pin control driver for iMX RT family
differences.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This modification is required to enable flash encryption.
Using hal implementation of spi_flash calls maintains
compability amongs different socs while offering
latest esp-idf enhancements.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
added support for NXP iMX RT600/RT500 to use to SDHC driver, with SD
subsystem. Tested with RT685 EVK
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable new USDHC driver for all RT10xx boards, since those will have
the SDHC driver selected by Kconfig
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.
This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.
There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.
Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.
Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.
Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.
Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.
This makes it possible to have code, independent of CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Adds LITEX_CSR_DATA_WIDTH option to Kconfig
Depending on its value appropriate read/write handling is used
for accessing CSR registers.
By using `>=` in preprocessor conditions it is somewhat future-proofed.
Doesn't touch `litex_read` and `litex_write` yet.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Add the appropriate hooks effectively replacing the old implementation
with the new one.
Also the stackguard wasn't properly enforced especially with the
usermode combination. This is now fixed.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
.module_init sections is used to keep all components constructor
functions.
Zephyr uses -ffunction-sections option which will create a section for
each function. Unfortunately, this creates a section named .module_init
for the function module_init() used to initialize the processing module
generic layer.
Thus, places module_init() in the constructor area named .module_init
which is wrong.
To avoid this we rename .module_init section for constructors to
.initcall.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
The linker script for the intel_s1000 was missing an include for the
snippets-rodata.ld file which is needed for any applications using the
`zephyr_linker_sources(RODATA <linker_script>)` cmake function.
Signed-off-by: Yuval Peress <peress@google.com>
The common linker script for cavs_v?? was missing an include for the
snippets-rodata.ld file which is needed for any applications using the
`zephyr_linker_source(RODATA <linker_script>)` cmake function.
Signed-off-by: Yuval Peress <peress@google.com>
This PR removes common-rom.ld section so that logging sections
can now be mapped into RAM area.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This PR removes common-rom.ld section so that logging sections
can now be mapped into RAM area.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This PR removes common-rom.ld section so that logging sections
can now be mapped into RAM area.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
In c5b59282d6, Kconfig option
CPU_CORTEX_M_HAS_CACHE was added only to a subset of stm32h7 soc
descriptions.
There is no reason not to extend to all socs as they all actually
feature a cache.
Fixes#45073
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
We no longer need to relocate the SDK power management
source file to SRAM. Instead specific functions from the
SDK file are relocated to the ramfunc section.
This commit fixes Issue#44670
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
CONFIG_RISCV_ATOMICS_ISA enables A extension.
CONFIG_RISCV_MUL_ISA enables M extension.
CONFIG_FLOAT_HARD enables F extension. (FPU)
Since we changed to use configuration options to enable extensions,
we no longer need to specify extensions using zephyr_compile_options.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
If a Zephyr binary is booted on the Zynq-7000 not via JTAG download,
but via u-boot's ELF boot function instead, Zephyr will have to revert
certain changes made by u-boot in order to boot properly:
- clear the ICache/DCache enable, branch prediction enable and
strict alignment enforcement enable bits in the SCTLR register.
By default, u-boot will also set up the MMU prior to Zephyr
doing so as well, this can be avoided by changing the u-boot
build configuration. Therefore, the MMU enable bit is not changed
at this point.
- set the VBAR register to 0. U-boot moves the interrupt vector
table to a non-standard location using the VBAR register (no
change is made by u-boot for SCTLR.V, only VBAR is changed
to a non-zero memory location).
Without these changes, Zephyr will crash upon the first context
switch at latest, when SVC is invoked and u-boot's vector table
is used rather than the vectors copied to address zero by Zephyr.
In order to perform these changes before coming anwhere near the
MMU / device driver / kernel initialization stages or even the
first context switch, the z_arm_platform_init hook is used, which
is now enabled for the Zynq via the Kconfig.defconfig file.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
pin control definitions present for LPC55xx are not generic to all LPC
IOCON controllers. Make pin control header file LPC55xx specific.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds hda link in and out drivers. The link in and link
out channels of HDA have small differences
with the host channels. Updates the existing
cavs_hda drivers and code to account for these
differences.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
all the consumers of the obsolete pinmux driver is
updated to use pinctrl API, this commit removes
the pinmux driver and assosciated sections.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Add pinctrl driver for CC13XX/CC26XX family of SoCs
to facilitate transition from pinmux to pinctrl.
`IOCPortConfigureSet()` from TI hal driverlib used to
implement the generic pinctrl driver.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
1.Declare the member type to match the kscan_it8xxx2_regs, so
we needn't to transform the local structure in the function.
2.Stop using DRV_CONFIG, DRV_DATA, DRV_REG macros.
3.Delete unused register defines.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
The Cache is an optional configuration of both the ARM Cortex-M7 and
Cortex-M55. Previously, it was just checking that it was just an M7
rather than knowing that the CPU actually was built with the cache.
Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
Zephyr kernel will always execute WFI in k_cpu_idle(), so access to TCM
will be gated. Keep the AHB clock enabled in sleep unless CONFIG_PM is
selected, to avoid this error.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Platform specific functions necessary to enable this feature were
implemented (z_xtensa_ptr_executable() and
z_xtensa_stack_ptr_is_sane() for Intel ADSP platforms.
Current implementation just ensures stack pointer and program counter
are within relevant areas defined in the linker scripts, without going
too fine grained.
Also, `.iram1` section, used by the backtrace code, also added to
Intel ADSP linker script.
Finally, update west manifest to use up-to-date SOF, which contains a
patch to fix build issues related to the linker changes.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Add MPU REGION_FLASH_SIZE definitions for 128M-512M flash sizes, to handle
arm SOCs with large flash regions.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
When we use a third-party or custom bootloader, there is also
need to remove the boot header. Change the select to imply,
so that the boot header can be removed by configuration when
MCUBoot is not used.
Signed-off-by: Frank Li <lgl88911@163.com>
Align definitions with definitions used in SOF upstream and define
CONFIG_XTENSA_WAITI_BUG for cAVS1.8, cAVS2.0 and cAVS2.5 platforms. On
these platforms, a workaround is needed with waiti.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
