Commit graph

6301 commits

Author SHA1 Message Date
Carlo Caione
56466a14e1 riscv: Decouple CLIC and PLIC
Try to decouple CLIC and PLIC as much as possible.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 14:31:39 +02:00
Carlo Caione
31c5dc2230 Kconfig: Introduce RISCV_HAS_CLIC
Introduce a new RISCV_HAS_CLIC symbol for platforms using CLIC,
reorganize the Kconfigs and make the Nuclei ECLIC depending on the new
symbol.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 14:31:39 +02:00
Julien Massot
08f5fb5cdb soc: arm: fvp_aemv8r_aarch32: define static mpu regions
Add static MPU regions for this SoC.
These regions will be initialized as static region during system boot.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
2022-07-11 11:17:02 +02:00
Flavio Ceolin
ad8ae7f735 dma: intel: Merge cavs and ace gpdma
cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-11 10:21:17 +02:00
Flavio Ceolin
b1abe896e6 intel_adsp: ace: Fix function return
zephyr/soc/xtensa/intel_adsp/ace_v1x/irq.c: In function
'z_soc_irq_is_enabled':

zephyr/soc/xtensa/intel_adsp/ace_v1x/irq.c:47:3: warning: 'return'
with no value, in function returning non-void [-Wreturn-type]

   47 |   return;

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-08 21:13:29 -04:00
Kumar Gala
a22ac090db soc: xtensa: intel_adsp: ace_v1x: irq: Convert to use DEVICE_DT_GET
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-08 20:03:32 +00:00
Kumar Gala
37fc9552e6 soc: xtensa: intel_adsp: irq: Convert to use DEVICE_DT_GET
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-08 20:03:32 +00:00
Kumar Gala
4faf362030 soc: apollo_lake: gpio: Drop use of DT_LABEL
Change APL_GPIO_DEV_* defines to be DT_NODELABELs instead of
"label" strings.  This lets us change users of these defines to
use DEVICE_DT_GET.

We update samples/board/up_squared/gpio_counter to use DEVICE_DT_GET
as part of this change.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-08 20:01:47 +00:00
Tom Burdick
572ccd531d intel_adsp: Use device tree to enable/disable each HDA driver
Uses the dt_compat_enabled Kconfig preprocessor to set defaults
for each HDA driver.

Each direction is uniquely selectable which can be useful when building
with SOF where only some directions may wish to be enabled at any given
time.

By default, given the device tree (intel_cavs.dtsi) only the host
directions are enabled but an overlay may adjust that as needed.

Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
2022-07-08 14:33:06 -04:00
Francois Ramu
c1782a096e soc: arm: new stm32f412Rx device
This adds a new stm32f412Rx in the list of stm32F4 devices.
The module stm32cube/stm32f4/soc/stm32f412rx.h exists

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-07-08 10:49:31 +02:00
Marc Herbert
08baba2520 soc/intel_adsp: cavstool: add support for DSP power state: D3
Change some behaviors when --log-only is passed in order to add support
for DSP power state: D3. This makes it possible to keep `cavstool
--log-only` running permanently in the "real-world" use case where the
Linux kernel loads the firmware and powers down audio when not in use.

More specifically:
- Do not disable D3 when using --log-only.
- Wait forever for the FW at boot time.
- Check live status when an invalid IPC is received and wait forever if
  not alive.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-07-08 10:45:44 +02:00
Marc Herbert
ef4cd76970 soc/intel_adsp: cavstool: new parameter wait_fw_entered(timeout_s)
Add a new timeout_s parameter that can also be 'None' = infinite.

No functional change. Required to add future support for DSP power
state: D3

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2022-07-08 10:45:44 +02:00
Mulin Chao
851e357aa4 pinctrl: npcx: add pinctrl support for psl pads
This CL introduces how to configure PSL (Power Switch Logic) pads
properties such as input detection mode/polarity, pin-muxing and so
on via pinctrl mechanism. It includes:

1. Add two pinctrl properties and their enums for PSL input
   detection configuration.
    psl-in-mode:
      - "level"
      - "mode"
    psl-in-pole:
      - "low-falling"
      - "high-rising"

2. Add macro functions to get PSL input detection and pin-muxing
   configurations from 'pinmux', 'psl-offset' abd 'psl-polarity'
   properties.

Here is an example to configure PSL_IN2 as the PSL detection input and
its mode and polarity.

/* A falling edge detection type for PSL_IN2 */
&psl_in2_gp00 {
	psl-in-mode = "edge";
	psl-in-pol = "low-falling";
};

A device will be introduced later which uses this pinctrl node to
configure PSL input detection settings and how to turn off VCC1 power
rail by PSL_OUT.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-07-07 14:12:52 +00:00
Joep Buruma
7e0fff24c7 drivers: pwm: add pwm driver for rpi_pico
Add pwm driver implementation for rpi pico family.
Adds myself as codeowner of drivers/pwm/*rpi_pico*

Signed-off-by: Joep Buruma <burumaj50@gmail.com>
2022-07-07 15:17:26 +02:00
Carlo Caione
fbe3436b36 esp32c3: Avoid circular header inclusion
Include arch.h from a different location to avoid missing symbol errors.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-07 10:00:20 +02:00
Carlo Caione
0e788b89a6 riscv: Use IRQ vector table for vectored mode
For vectored interrupts use the generated IRQ vector table instead of
relying on a custom-generated table.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-07 10:00:20 +02:00
Pieter De Gendt
e381170282 uart_pipe: Remove obsolete UART_PIPE_ON_DEV_NAME Kconfig
The UART pipe device is selected with devicetree chosen zephyr,uart-pipe

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2022-07-07 09:59:49 +02:00
Flavio Ceolin
158a87018c intel: adsp: Simplify PM
Both idle and suspend states were just being used to set the cpu
idle. That is not necessary, if the pm policy does not find a suitable
power state the kernel automatically calls k_cpu_idle().

This remove unnecessary code and the weirdness of having
min-residency-us set to 0 and other arbitrary values.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-07 02:10:11 -04:00
Enjia Mai
faff3f7ecc soc: xtensa: partial fix of socket misuse and refine the code
1. Improve the firmware transfer reliability by fixing the misuse
of the socket. Fix the most frequent occurence of the common `recv()`
bug described here:

https://docs.python.org/3/howto/sockets.html#using-a-socket

The longer term fix is to switch to a higher level API like Python
Remote Objects.

2. Not rely on the client's command to disconnect. Previously we
rely on the SIGINT to send stop_command to the server, but it does
not work well in some environments. Refine the whole logic and the
sever disconnect service by checking if the client is alive or not.

These changes make the client-server-based cavstool more stable.

Fixes #46864

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-07-06 20:38:41 -04:00
Andrey Borisovich
e0b1d81acb soc: intel_adsp: added casting for C++ compiler in soc.h
Header soc.h is included during C++ source file compilation
and required adding C++ casts as implicit casting from void*
is forbidden. Fixed minor warning comparing signed with unsigned
integer.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Andrey Borisovich
aa253d9ab1 soc: intel_adsp: reading HP SRAM banks count for ACE1X from Devicetree
Replaced hardcoded for intel_adsp_ace15_mtpm board
HP_MEMORY_BANKS value used in SOF code with generic approach -
using PLATFORM_HPSRAM_EBB_COUNT read from Devicetree.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Flavio Ceolin
92725e3102 soc: adsp: sram: Assorted cosmetic fixes
General code style fixes.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-06 15:11:07 -04:00
Flavio Ceolin
7291c518a0 soc: ace: Organizing include headers
Properly prefixing some include files with "zephyr", also organizing
the order they are included.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-06 15:11:07 -04:00
Flavio Ceolin
65fbfcd480 soc: ace: Move power management to its own file
Move power management hooks to its own C file.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-06 15:11:07 -04:00
Flavio Ceolin
e4a3e2d8b6 intel_adsp: Unify cavs and ace timers
These two timers were sharing pretty much the same code. Actually
mtl timer was a "superset" of cavs timer. Just merge them into a
single one called intel audio dsp timer (intel_adsp_timer).

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-07-06 15:11:07 -04:00
Andrey Borisovich
e0e2dbf6f0 soc: ace1x: provided register names to addresses
Provided register names to hardcoded addresses in ace_v1x-regs
header.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Anas Nashif
8792dd800d soc: ace1.x: use common code
Do not duplicate code in new SoC and reuse code from intel_adsp/common.
Move SRAM code into own file in common code and setup SRAM in soc for
MTL platform.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-06 15:11:07 -04:00
Tomasz Leman
0b15a8d3ef soc: ace_v1x: pm_state_exit_post_ops implementation
Implementation of the function used during the exit from the lower power
states.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-07-06 15:11:07 -04:00
Tomasz Leman
8940b9cae5 soc: ace_v1x: pm_state_set implementation
This patch implements pm_state_set function for ACE platforms.

This is initial implementation and only includes the basic handling of
PM_STATE_SOFT_OFF.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-07-06 15:11:07 -04:00
Tomasz Leman
cc9f82de44 soc: ace_v1x: soc_adsp_halt_cpu implementation
This patch add soc_adsp_halt_cpu implementation for ace. Function disable
power and check CPA status to report success. Function should be used only
for secondary cores and can be executed only from primary core.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2022-07-06 15:11:07 -04:00
Rafal Redzimski
b49d794966 ace: multiprocessing: add polling for core powered up confirmation
Poll for CPA bit by which HW confirms that the core has been powered up.

Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Rafal Redzimski
090b01e73c ace: multiprocessing: enable secondary core boot through ROM
Add ace/mtl rom flags definitions.
Set the flags in battr to indicate to rom that it should execute
secondary core procedure.

Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Anas Nashif
b330a05539 intel_adsp: add a new series to support Meteorlake
Meteorlake support as part of the Intel ADSP family.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Enjia Mai <enjia.mai@intel.com>
Co-authored-by: Flavio Ceolin <flavio.ceolin@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Bonislawski Adrian <adrian.bonislawski@intel.com>
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
2022-07-06 15:11:07 -04:00
Anas Nashif
782b083686 soc: add mising braces to single line if statements
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-06 11:00:45 -04:00
Alexandre Duchesne
1561b1046f soc: arm: gigadevice: Initial support for gd32f470
add initial support for gd32f470 SoC

Signed-off-by: Alexandre Duchesne <alexandre.duchesne@rtone.fr>
2022-07-06 13:22:25 +02:00
Ruibin Chang
dc3f29f67f ITE tests/kernel/sleep: tune CONFIG_SYS_CLOCK_TICKS_PER_SEC down
We need more time to run codes because of the performance,
so I tune CONFIG_SYS_CLOCK_TICKS_PER_SEC down to reduce
the times of running k_usleep(1), then it can pass test_usleep().

Verified by follow test pattern:
west build -p always -b it8xxx2_evb tests/kernel/sleep

fixes #46208

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2022-07-05 11:29:43 +00:00
Christian Taedcke
e71c2d1893 boards: efm32pg_stk3402a: Add minimal pwm support
With this additions samples/basic/blinky_pwm works.
LED0 is used as pwm output.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2022-07-04 15:51:11 +02:00
Alex Sergeev
f7f35af277 soc: gd32: Add HAS_SEGGER_RTT
Enable SEGGER RTT for GigaDevice family.

Signed-off-by: Alex Sergeev <asergeev@carbonrobotics.com>
2022-07-04 09:50:35 +02:00
Enjia Mai
a1e388ea2e soc: xtensa: keep the CAVS old flasher still works
Keep the cavstwist.sh it is still working by specifying an
environment variable when CAVS_OLD_FLASHER is set. Provide
a fallback once the client-server-based tool does not work
well in some conditions.

Signed-off-by: Enjia Mai <enjia.mai@intel.com>
2022-07-02 06:06:19 -04:00
Kumar Gala
287acdbb9d i2c: sam0: Set driver Kconfig default based on devicetree
Change Kconfig default to be based on if the devicetree has the
atmel,i2c-sam0 driver enabled.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-01 15:05:55 -05:00
Kumar Gala
d200321767 video: mcux_csi: Set driver Kconfig default based on devicetree
Change Kconfig default to be based on if the devicetree has the
nxp,imx-csi driver enabled.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-01 14:56:33 -05:00
Daniel Leung
1277c38797 cavs: disable timer interrupt on cpu power off
Since the timer interrupt is delivered to all cores at the same
time, it needs to be disabled (or masked) to prevent it from
waking a suspended CPU core.

Note that there is no need to re-enable (unmask) timer
interrupt separately as it is being taken care of in
smp_timer_init() when the CPU re-inits itself.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-07-01 14:04:50 -04:00
Guennadi Liakhovetski
3748bdcad6 xtensa: return to idle() when booting sporadically
To power down secondary cores on cAVS 2.5 platforms the primary core
enables the power-saving mode for the respective secondary core and
waits until that core enters idle() and executes the waiti
instruction at which point the core should enter a lower-power mode.
However, that core can then also automatically wake up and execute
its reset path if, e.g. an interrupt is delivered to it. However, it
isn't entirely clear which events are able to wake up cores from that
state. Disabling interrupts on the interrupt controller didn't seem
to prevent that from happening completely. In particular a specific
ADL notebook seems to be susceptible to this problem. Checking for
such sporadic boots and returning to idle fixes the problem.

BugLink: https://github.com/zephyrproject-rtos/zephyr/issues/46372
BugLink: https://github.com/thesofproject/sof/issues/5733
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2022-07-01 14:04:50 -04:00
Bartosz Bilas
33a4c78699 soc: select HAS_MCUX_XBARA for MIMXRT1062
Select HAS_MCUX_XBARA Kconfig symbol for MIMXRT1062,
since the XBARA Inter-Peripheral Crossbar Switch peripheral is present
on this SOC.

Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
2022-07-01 16:23:11 +00:00
Glauber Maroto Ferreira
fb919a75ba soc: esp32/s2/c3: pinctrl: update pin init macros
Updates pin initialization macros to make use
of pin grouping.

Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2022-07-01 16:22:18 +00:00
Jay Vasanth
e74978cc03 microchip: mec: zephyr spi image generation
Added mchp mec zephyr image generator python script. It takes
zephyr.bin as input and produces zephyr.mchp.bin.
The default behavior is to not pad to SPI flash size.
(Enable through CONFIG_MCHP_MEC_UNSIGNED_HEADER=y and
CONFIG_MCHP_MEC_HEADER_FLASH_SIZE_256K=y)

zephyr.mchp.bin is composed of:
1. First 4KB contains TAG at offset 0 and header at offset 0x100
2. Offset 0x1000 is the start of zephyr.bin which has been padded
to a multiple of 128 bytes.
3. Boot-ROM EC Info Block (128 bytes)
4. Boot-ROM Co-Signature Block (96 bytes)
5. Boot-ROM trailer (160 bytes) contains the SHA-384 digest of 2-4.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-07-01 11:35:13 +02:00
Bartosz Bilas
091a54202a soc: arm: nxp_imx: rt: add new MIMXRT1062CVJ5B part number
Add missing MIMXRT1062CVJ5B SOC.

Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
2022-06-30 19:50:03 +00:00
Bartosz Bilas
dcf2d4d542 soc: arm: nxp_imx: rt: add new MIMXRT1062CVJ5A part number
Add missing MIMXRT1062CVJ5A SOC.

Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
2022-06-30 19:50:03 +00:00
Alexandre Duchesne
7109e7dc20 soc: st_stm32f7: Add stm32f750xx SoC
add initial support for STM32F750xx SoC

Signed-off-by: Alexandre Duchesne <alexandre.duchesne@rtone.fr>
2022-06-30 13:41:06 +00:00
Ederson de Souza
afed5e4010 soc/xtensa/intel_adsp/tools: Dial back stream reset sleep
A full second is too much, and since "Ack local interrupt before
processing IPC" patch, it doesn't seem necessary. This whole second
wait would break tests that log too much content, as the firmware
is already running during the reset - and the host script wouldn't read
the contents, thus some of the logs would be overwritten.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-06-30 06:13:30 -04:00