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soc: modifications for cyw920829m2evk_02 mpu regions

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- Modifcation to mpu information, in relation to functionality
	  in userspace

Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
This commit is contained in:
McAtee Maxwell 2025-01-22 12:29:51 -08:00 • committed by Benjamin Cabé
commit 55ec415793
4 changed files with 36 additions and 35 deletions
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1
soc/infineon/cat1b/cyw20829/CMakeLists.txt
View file

@ -3,6 +3,7 @@
zephyr_sources(soc.c)
zephyr_sources(app_header.c)
zephyr_sources(mpu_regions.c)
zephyr_include_directories(.)
zephyr_sources_ifdef(CONFIG_PM power.c)

1
soc/infineon/cat1b/cyw20829/Kconfig
View file

@ -8,6 +8,7 @@
config SOC_SERIES_CYW20829
select ARM
select CPU_HAS_ARM_MPU
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
select CPU_CORTEX_M33
select DYNAMIC_INTERRUPTS
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE

34
soc/infineon/cat1b/cyw20829/mpu_regions.c Normal file
View file

@ -0,0 +1,34 @@
/* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#define BOOTSTRAP_RAM_BASE_ADDRESS DT_REG_ADDR(DT_NODELABEL(sram_bootstrap))
#define BOOTSTRAP_RAM_SIZE DT_REG_SIZE(DT_NODELABEL(sram_bootstrap))
#define REGION_BOOTSTRAP_RAM_ATTR(base, size) \
{ \
.rbar = FULL_ACCESS_Msk | NON_SHAREABLE_Msk, \
.mair_idx = MPU_MAIR_INDEX_SRAM, \
.r_limit = REGION_LIMIT_ADDR(base, size), \
}
static const struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("FLASH", CONFIG_FLASH_BASE_ADDRESS,
REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, CONFIG_FLASH_SIZE * 1024)),
MPU_REGION_ENTRY("SRAM", CONFIG_SRAM_BASE_ADDRESS,
REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, CONFIG_SRAM_SIZE * 1024)),
MPU_REGION_ENTRY("BOOTSTRAP_RAM", BOOTSTRAP_RAM_BASE_ADDRESS,
REGION_BOOTSTRAP_RAM_ATTR(BOOTSTRAP_RAM_BASE_ADDRESS, BOOTSTRAP_RAM_SIZE)),
};
const struct arm_mpu_config mpu_config = {
.num_regions = ARRAY_SIZE(mpu_regions),
.mpu_regions = mpu_regions,
};

35
soc/infineon/cat1b/cyw20829/soc.c
View file

@ -54,43 +54,8 @@ cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t *config, cy_israddres
return(status);
}
/*
* This function will allow execute from sram region. This is needed only for
* this sample because by default all soc will disable the execute from SRAM.
* An application that requires that the code be executed from SRAM will have
* to configure the region appropriately in arm_mpu_regions.c.
*/
#ifdef CONFIG_ARM_MPU
#include <cmsis_core.h>
void disable_mpu_rasr_xn(void)
{
uint32_t index;
/*
* Kept the max index as 8(irrespective of soc) because the sram would
* most likely be set at index 2.
*/
for (index = 0U; index < 8; index++) {
MPU->RNR = index;
#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
if (MPU->RBAR & MPU_RBAR_XN_Msk) {
MPU->RBAR ^= MPU_RBAR_XN_Msk;
}
#else
if (MPU->RASR & MPU_RASR_XN_Msk) {
MPU->RASR ^= MPU_RASR_XN_Msk;
}
#endif /* CONFIG_ARMV8_M_BASELINE || CONFIG_ARMV8_M_MAINLINE */
}
}
#endif /* CONFIG_ARM_MPU */
void soc_early_init_hook(void)
{
#ifdef CONFIG_ARM_MPU
disable_mpu_rasr_xn();
#endif /* CONFIG_ARM_MPU */
/* Initializes the system */
SystemInit();