soc: modifications for cyw920829m2evk_02 mpu regions
- Modifcation to mpu information, in relation to functionality in userspace Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
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4 changed files with 36 additions and 35 deletions
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@ -3,6 +3,7 @@
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zephyr_sources(soc.c)
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zephyr_sources(app_header.c)
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zephyr_sources(mpu_regions.c)
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zephyr_include_directories(.)
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zephyr_sources_ifdef(CONFIG_PM power.c)
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@ -8,6 +8,7 @@
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config SOC_SERIES_CYW20829
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select ARM
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select CPU_HAS_ARM_MPU
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select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
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select CPU_CORTEX_M33
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select DYNAMIC_INTERRUPTS
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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34
soc/infineon/cat1b/cyw20829/mpu_regions.c
Normal file
34
soc/infineon/cat1b/cyw20829/mpu_regions.c
Normal file
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@ -0,0 +1,34 @@
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/* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
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* an affiliate of Cypress Semiconductor Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
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#define BOOTSTRAP_RAM_BASE_ADDRESS DT_REG_ADDR(DT_NODELABEL(sram_bootstrap))
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#define BOOTSTRAP_RAM_SIZE DT_REG_SIZE(DT_NODELABEL(sram_bootstrap))
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#define REGION_BOOTSTRAP_RAM_ATTR(base, size) \
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{ \
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.rbar = FULL_ACCESS_Msk | NON_SHAREABLE_Msk, \
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.mair_idx = MPU_MAIR_INDEX_SRAM, \
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.r_limit = REGION_LIMIT_ADDR(base, size), \
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}
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static const struct arm_mpu_region mpu_regions[] = {
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MPU_REGION_ENTRY("FLASH", CONFIG_FLASH_BASE_ADDRESS,
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REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, CONFIG_FLASH_SIZE * 1024)),
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MPU_REGION_ENTRY("SRAM", CONFIG_SRAM_BASE_ADDRESS,
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REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, CONFIG_SRAM_SIZE * 1024)),
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MPU_REGION_ENTRY("BOOTSTRAP_RAM", BOOTSTRAP_RAM_BASE_ADDRESS,
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REGION_BOOTSTRAP_RAM_ATTR(BOOTSTRAP_RAM_BASE_ADDRESS, BOOTSTRAP_RAM_SIZE)),
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};
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const struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};
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@ -54,43 +54,8 @@ cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t *config, cy_israddres
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return(status);
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}
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/*
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* This function will allow execute from sram region. This is needed only for
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* this sample because by default all soc will disable the execute from SRAM.
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* An application that requires that the code be executed from SRAM will have
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* to configure the region appropriately in arm_mpu_regions.c.
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*/
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#ifdef CONFIG_ARM_MPU
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#include <cmsis_core.h>
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void disable_mpu_rasr_xn(void)
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{
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uint32_t index;
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/*
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* Kept the max index as 8(irrespective of soc) because the sram would
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* most likely be set at index 2.
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*/
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for (index = 0U; index < 8; index++) {
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MPU->RNR = index;
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#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
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if (MPU->RBAR & MPU_RBAR_XN_Msk) {
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MPU->RBAR ^= MPU_RBAR_XN_Msk;
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}
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#else
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if (MPU->RASR & MPU_RASR_XN_Msk) {
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MPU->RASR ^= MPU_RASR_XN_Msk;
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}
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#endif /* CONFIG_ARMV8_M_BASELINE || CONFIG_ARMV8_M_MAINLINE */
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}
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}
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#endif /* CONFIG_ARM_MPU */
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void soc_early_init_hook(void)
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{
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#ifdef CONFIG_ARM_MPU
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disable_mpu_rasr_xn();
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#endif /* CONFIG_ARM_MPU */
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/* Initializes the system */
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SystemInit();
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