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dts: arm: stm32N6 reg definition for the st,stm32-xspi compatible

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The st,stm32-xspi compatible is defining the reg property
with the register address and size at first index
followed by the external memory base address and max allocated
size. For the stm32N6 serie,
xspi1 is addressing max 256 MBytes from 0x90000000
xspi2 is addressing max 256 MBytes from 0x70000000

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2025-04-15 11:59:08 +02:00 • committed by Benjamin Cabé
commit a6d652e158
1 changed files with 4 additions and 4 deletions
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8
dts/arm/st/n6/stm32n6.dtsi
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@ -687,27 +687,27 @@
xspi1: xspi@58025000 {
compatible = "st,stm32-xspi";
reg = <0x58025000 0x1000>;
reg = <0x58025000 0x1000>, <0x90000000 DT_SIZE_M(256)>;
interrupts = <170 0>;
clock-names = "xspix", "xspi-ker", "xspi-mgr";
clocks = <&rcc STM32_CLOCK(AHB5, 5)>,
<&rcc STM32_SRC_HCLK5 XSPI1_SEL(0)>,
<&rcc STM32_CLOCK(AHB5, 13)>;
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
xspi2: spi@5802a000 {
compatible = "st,stm32-xspi";
reg = <0x5802A000 0x1000>;
reg = <0x5802A000 0x1000>, <0x70000000 DT_SIZE_M(256)>;
interrupts = <171 0>;
clock-names = "xspix", "xspi-ker", "xspi-mgr";
clocks = <&rcc STM32_CLOCK(AHB5, 12)>,
<&rcc STM32_SRC_HCLK5 XSPI2_SEL(0)>,
<&rcc STM32_CLOCK(AHB5, 13)>;
#address-cells = <1>;
#size-cells = <1>;
#size-cells = <0>;
status = "disabled";
};