Add minimal support for the aesc silicon UART IP core.
This core includes an internal clock divider and supports flexible
frame configurations, allowing for variable data length, parity, and
stop bit settings.
The current driver version does not support interrupts.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
aesc silicon is a startup focused on developing open-source
silicon solutions.
Link: https://github.com/aesc-silicon/ElemRV
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Rename the frac-v PLL binding into fracn in order to make it
consistent with other STM32 PLL bindings.
This commit also correct the range which should be 0 - 8191.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Depending on the PLL, all DIV-P / DIV-Q and DIV-R are available
on STM32MP13 PLLs.
Adjust valid range in order to be able to set for all 4 PLLs.
Clarify DT properties description.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
This commit adds following updates to MAX32650 SoC:
- Divide SRAM to sections according to UG.
- Add DMA and SPI nodes
- Add WDT nodes without adding clock property
- Include dma binding to SoC dts file.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
Signed-off-by: Burak Babaoglu <burak.babaoglu@analog.com>
This commit changes clock property of watchdog to optional and updates
driver according to this change.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
Add an led_strip driver for the modulino smartleds module. This is a
pluggable I2C board with 8 addressable RGB LEDs
The I2C protocol is implemented on an microcontroller on the modulino
board itself, the firmware for that is open source and can be updated
using an Arduino sketch:
Link: https://github.com/arduino/node_modulino_firmware
Link: https://github.com/arduino-libraries/Modulino
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add an input driver for the modulino buttons module. This is a pluggable
I2C board implementing three buttons and three LEDs, the I2C protocol is
implemented on a microcontroller on the modulino board itself, the
firmware for that is open source and can be updated using an Arduino
sketch:
Link: https://github.com/arduino/node_modulino_firmware
Link: https://github.com/arduino-libraries/Modulino
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Implement the video API frame interval handling in order
to control the framerate of capture.
This allow to remove the capture-rate DT property as well.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
With the addition of the dma property within the soc dtsi, it is
no more necessary to add it within the board dts.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Usage of dma is mandatory for the dcmi and this property is
tightly coupled with the soc itself since the configuration of
the dma depends on the source/destination, and the request line
is also fixed for an ip.
Instead of having to always have the dma property part of the
board or shield dts/overlay, add the dma property into the
dcmi node of the stm32h7.dtsi.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Update the bindings of the stm32-dcmi driver rely on
properties described within the endpoints and already
detailed within the video-interfaces.yaml.
With that, several properties located at the node root
are now moved into the port / endpoint:
sensor -> endpoint: remote-endpoint-label
vsync-active -> endpoint: vsync-active
hsync-active -> endpoint: hsync-active
pixelclk-active -> endpoint: pclk-sample
bus-width -> endpoint: bus-width
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Changed to define ambiq spi/i2c dma mode as a binding property
instead of kconfig macros, making it more flexible for different
spi/i2c instances.
Signed-off-by: Hao Luo <hluo@ambiq.com>
Most SPI NOR flash devices support a "fast read" command which uses
dummy bits between the address and the start of the data transfer. In
many cases, the maximum SPI clock speed of the device is lower for the
regular read command due to the limited time between the address and
data phases, so using the fast read command will remove this restriction
and allow for faster transfers.
Add a device tree flag to indicate that fast reads should be used for
the device.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Some Micron (and possibly other) SPI NOR devices implement a flag status
register which provides more information on the success/failure of erase
and program operations. In addition to better error checking, some of
these devices actually don't function properly if the flag status
register is not read after a program operation (subsequent reads will
only return 0xFF bytes).
Add a device tree parameter to indicate that the flag status register is
supported. When specified, the flag status register will be used for
ready/error checks rather than the standard status register.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add an erased-undefined property for Renesas RA series MCUS
data flash that will read back undefined values when erased
Signed-off-by: Jeremy Dick <jdick@pivotint.com>
Enables using the whole flash on CH32V208
This also involves limiting frequency of the CPU to 120Mhz
from 144Mhz to meet recommendations.
Signed-off-by: Camille BAUD <mail@massdriver.space>
Move backlight i2c controller address into DTS configuration
to be able to use jhd1313 driver for dfrobot's LCD1602.
Signed-off-by: Leon Mariotto <leon2mariotto@gmail.com>
This commit introduces a new driver for a common GPIO-driven 7-segment
display. supporting both common anode and common cathode configurations.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Add CAN driver support for Renesas RZ/G3S
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
it8xxx2 pwm driver does not handle "pwm-output-frequency" property,
so setting the property in borad.dts is useless.
About PWM output frequency, it can be set by pwm-cells "period",
"pwm-output-frequency" is really redundant.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
The CH32V006 is part of the CH32V00x series of 32 bit RISC-V
microcontrollers. This series is an evolution of the CH32V003 which
was used as a basis for this Devicetree definition.
Compared to the CH32V003, thie CH32V006 has an extra GPIO port (PB),
an extra UART (UART2), 8 KiB of RAM, 62 KiB of flash, and uses the
QingKe V2C core.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The CH32V006 and others in the CH32V00x series are an evolution of the
CH32V003 and use different remap offsets for the various peripherals.
In the same way as the CH32V20x, fork the CH32V003 driver and add
CH32V00x support.
Signed-off-by: Michael Hope <michaelh@juju.nz>
