Add support for Silergy SY6974B 3A single-cell Li-Ion switching battery
charger with I2C control, USB BC1.2 detection, OTG boost and power-path
management.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
Increase the minimum residency value to 1.5ms since the minimum threshold
is 1070us and depends on max-hs-startup-time (default value: 780us).
Therefore, a safe margin is 1500us to support other values for
max-hs-startup-time.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Add no-3-3-v and no-3-0-v boolean properties to the NXP USDHC binding.
These are needed for boards where the SD host I/O voltage domain is
1.8V only and does not support 3.3V or 3.0V signaling.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Add support for the ODRIVE (output drive) field at bits 12-13 of the
IOPCTL register on RT7XX. This field controls the transmitter current
drive impedance selection (100/66/50/33 ohm).
- Add nxp,drive-current property to the rt-iocon-pinctrl binding
- Add IOPCTL_PIO_ODRIVE macro to pinctrl_soc.h
- Extend pin config mask from 0xFFF to 0x3FFF to include ODRIVE bits
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Add support for multiple plane devices to the SPI NAND driver.
This includes adding a new plane-bytes property to the device
tree bindings, which indicates the size of each plane in the
flash device. For devices with a single plane, this should be
set to the same value as size-bytes.
Some devices require the plane address as part of read and/or
program commands. For these devices, the new has-read-plane-select
and has-program-plane-select properties can be set to indicate
that the driver should include the plane address in read and
program commands.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
For devices that does not have interrupt pin, default to polling mode
instead.
Polling period can be configured through
CONFIG_ETH_W5500_POLL_PERIOD.
Signed-off-by: Aiman Mazlan <mohammad.aiman@stratusauto.com>
Add zephyr,mspi-peripheral-device devicetree binding to describe an MSPI
bus peripheral (e.g. another SoC in peripheral mode or an external
peripheral) that the local controller talks to. No driver is required;
use for SoC-to-SoC links or application-defined peripherals.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
commit 9b2593b8c5 has changed the internal
ili9xxx driver color config from setting BGR mode (Blue-Red channels
swap, not pixel format byte-swap) by default, to conditioning it on the
use of PIXEL_FORMAT_BGR_565 (ILI9XXX_PIXEL_FORMAT_BGR565 in devicetree),
but without updating all boards/shields to use
ILI9XXX_PIXEL_FORMAT_BGR565 to preserve their old config.
Then commit 69e353904c replaced
ILI9XXX_PIXEL_FORMAT_BGR565 to PANEL_PIXEL_FORMAT_BGR565.
Later, commit b13d9a0510 renamed
PANEL_PIXEL_FORMAT_BGR565 to PANEL_PIXEL_FORMAT_RGB565X, and defined it
as "Byte swapped version of the PIXEL_FORMAT_RGB_565 format", which is
different from how it was interpreted by ili9xxx devices (B/R channel
swapped format).
The fix for this mess is:
- separate BGR mode (B/R channel swap) setting for ili9xxx from pixel
format,
- restore the initial driver config that sets BGR mode by default, in
order to not break in-tree and out-of-tree panels that relied on that
behavior,
- introduce a DT property that allows disabling BGR mode.
A bonus enhancement is to set BGR mode in ili9xxx driver outside
set_orientation() function, since they are unrelated.
Fixes https://github.com/zephyrproject-rtos/zephyr/issues/105521
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
- Add scmi clocks for both RTI0 and RTI1 nodes.
- Add reset-capable property so that the driver can configure
reset mode supported by AM62L boards.
Signed-off-by: Sunil Hegde <s-hegde3@ti.com>
Currently all boards use the driver which only configures
NMI mode for a window violation. With this change:
- If interrupts are present in the DT, hardware is NMI capable
- If reset-capable property is true, hardware can generate a reset
By this we can define the capabilities of the hardware based on
which the driver can configure NMI or Reset mode. The existing
nodes in the boards which support NMI will not be affected
since all of them provide IRQ numbers.
Signed-off-by: Sunil Hegde <s-hegde3@ti.com>
Use priority 0 (the lowest) at SoC DTSI level for all interrupts such that
they are all equal. The user is responsible for tuning priorities at board
level depending on use case.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add support for the Trasna LEXI-R10 cellular modem in the generic
cellular module driver, starting from similar cellular modules
(e.g., LARA-R6 and/or SARA-R4).
LEXI-R10 is an ultra-compact LTE Cat-1bis module, designed for
IoT and M2M applications, featuring integrated IP connectivity
and clients.
The binding identifies the UART of the device.
Signed-off-by: Mattia Rebato <mattia.rebato@trasna.io>
The IIC controller does not implement the recover_bus API. When a
peripheral holds SDA low, the bus becomes stuck and cannot be
recovered without intervention (such as a reset).
Add bus recovery support via GPIO bitbanging. When enabled via
`CONFIG_I2C_RENESAS_RA_BUS_RECOVERY`, the driver reconfigures
the SCL and SDA pins as GPIOs, clocks out 9 pulses on SCL to force
the peripheral to release SDA, then restores the pins to the hardware
I2C controller via pinctrl.
Add scl-gpios and sda-gpios devicetree properties to identify
the GPIO lines used for recovery.
Signed-off-by: Andres Hernandez <andres.a.h@outlook.com>
The LE910C1TX is an Ultra‑compact LTE Cat 1 module designed for IoT and
M2M applications, featuring integrated IP connectivity and the Telit
xE910 unified form factor.
The binding identifies the UART device, the power GPIO and the reset
GPIO lines.
Signed-off-by: Luca Impagliazzo <Luca.Impagliazzo@telit.com>
Add support for toggling a reset line during GPIO
initialization when a reset controller is available
in the device tree.
Signed-off-by: Muhammad Waleed Badar <muhammadx.waleedbadar@altera.com>
'sitronix,st7789v' panel controller driver is using ST7789V_PIXEL_FORMAT
Kconfig option to set pixel format, which is ignored in the device
initialization which instead uses DT colmod property to set the pixel
format.
Remove the Kconfig option and colmod DT property, and instead use the
standard pixel-format DT property to set the colmod register.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Add device tree binding for ONFI-compatible NAND flash devices connected
to NXP FlexSPI controllers. The binding extends the base FlexSPI device
binding and includes soc-nv-flash.yaml to inherit the write-block-size
and erase-block-size properties. Device geometry (page size, pages per
block, total capacity) is probed at runtime from the ONFI parameter page.
Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
Add SPI peripheral nodes to the MSPM0 family dtsi to
enable spi support for the G and L series.
Signed-off-by: Santhosh Charles <santhosh@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
Add devicetree bindings for the TI MSPM0 SPI module.
Signed-off-by: Santhosh Charles <santhosh@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
Introduce a single "bflb,bt-hci" compatible for all Bouffalo Lab
on-chip BLE controllers, replacing the per-SoC "bflb,bl70x-bt-hci"
and "bflb,bl70xl-bt-hci" strings. Update both bl70x.dtsi and
bl70xl.dtsi to use the unified compatible.
Add the bt-hci node (disabled by default) to bl70xl.dtsi for
boards that enable BLE support.
Promote the retram node (HBN RAM at 0x40010000) to a proper
zephyr,memory-region so BLE vendor blob sections (.hbn_code,
.retention_noinit) can be placed there by the linker.
Signed-off-by: William Markezana <william.markezana@gmail.com>
The GPIO Ports E&G are available on STM32H5x3.
Having them in the device tree by default is nice.
Signed-off-by: Raghuveer Kasaraneni <raghu@kasara.net>
ESP32-C2 and ESP32-C3 implement the zifencei extension (fence.i)
but their device trees declared only "i", "m", "c", "zicsr".
Adding zifencei selects rv32im_zicsr_zifencei/ilp32, the atomic-free
multilib, fixing illegal instruction faults on picolibc paths that
touch stdio locking.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
RTS5912 supports the SWJ interface,
which configures related GPIOs during EC initialization.
Disable the SWJ interface to ensure the GPIOs
remain in the state defined in the device tree.
Signed-off-by: Elmo Lan <elmo_lan@realtek.com>
OTP address was wrong (bad copy/paste from another series). This commit
sets it to the correct value.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Extends ADP5360 Regulator API support to the existing
ADP5360 Buck and Buck Boost Regulator.
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
Co-authored-by: Francis Roi Manabat <francisroi.manabat@analog.com>
Implements fuel gauge subsystem for ADP5360 MFD driver.
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
Co-authored-by: Francis Roi Manabat <francisroi.manabat@analog.com>
Adds Charger subsystem support for the ADP5360 MFD device.
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
Co-authored-by: Francis Roi Manabat <francisroi.manabat@analog.com>
Implements I2C communication used by drivers under this parent device,
interrupt support, supervisory data configuration,
and power management subsystem API.
Signed-off-by: Jan Carlo Roleda <jancarlo.roleda@analog.com>
Co-authored-by: Francis Roi Manabat <francisroi.manabat@analog.com>
Updated PCR and GIRQ properties to use new macros.
Updated symcr and romapi node for mec174x/5x/165xb
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
RM0481 Rev 4 documents the Ethernet PTP timestamp clock as a dedicated
reference clock (`clk_ptp_ref_i`), not the `eth_hclk` bus clock.
Table 115 ("Kernel clock distribution overview", p. 470/3154) lists
`ETH (ptp)` on `pll1_q_ck`, and the IEEE 1588 section states that the
64-bit PTP time is updated from `clk_ptp_ref_i`.
Add an explicit `mac-clk-ptp` clock for STM32H5 sourced from
`STM32_SRC_PLL1_Q`, use that clock rate for PTP addend programming.
Because this change introduces source-clock configuration for STM32
Ethernet clocks, update the STM32H7 DWMAC path as well: use
`clock_control_configure()` for source clocks such as `eth-ker`, while
keeping `clock_control_on()` for gated clocks.
Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
