This commit enhances the SAR ADC driver by adding
support for clock frequency selection. The clock
frequency can now be configured via the devicetree,
allowing for better optimization of ADC performance
based on application requirements.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
This PR combines node content in the same file spread over multiple
node definitions.
This PR has not funtional changes to the boards
Signed-off-by: Kyle Bonnici <kylebonnici@hotmail.com>
Add the inter-processor interrupt (IPI) nodes to the device tree for the
Versal Gen2 platform, as per Versal Gen2 Technical Ref Manual (AM026)
Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>
Add the inter-processor interrupt (IPI) nodes to the device tree for the
Versal-NET platform, as per Versal-NET Technical Reference Manual (TRM).
Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>
Add device tree bindings for the AMD-Xilinx Inter Processor Interrupts
(IPI) mailbox.
The IPI architecture allows the passing of messages across the system
without the complications of autonomous read-write transactions and
polling inefficiency. The notification of the interrupt is also
possible without message buffers on some platforms. Some IPI channels
are hard-wired to particular core while others can be configured to
assign to any core on AMD-Xilinx heterogenous multiprocessor platform.
Signed-off-by: Ajay Neeli <ajay.neeli@amd.com>
Add CAN FD support for MCXN SOC family, including mcxn23x, mcxn94x
and mcxn54x.
Tested with tests/drivers/can.
Fixes#91138
Signed-off-by: William Tang <william.tang@nxp.com>
Fix incorrect LPTMR prescaler/glitch filter mapping that led to wrong
frequency calculation and wrong hardware configuration.
- Calculate effective counter frequency correctly:
* Time Counter mode: divide by 2^(value + 1)
* Pulse Counter mode: divide by 2^value
- Map prescale-glitch-filter directly to the HAL enum (no offset math)
- Add prescale-glitch-filter-bypass DT boolean (default false)
- Restrict prescale-glitch-filter to 0..15 and update bindings/DTS users
- Add build-time validation for Pulse mode (value 0 requires bypass)
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add the `number-of-mb` and `number-of-mb-fd` device tree property to
all the NXP FlexCAN controller nodes across various SoC families to
specify the maximum number of 8-byte and 64-byte payload message
buffers supported by each FlexCAN instance.
This change updates device tree source files for multiple NXP SoC
families including Kinetis K6x, RT10xx, RT11xx, RT118x, MCX, S32K,
S32Z, and i.MX8MP/i.MX93 series. The property values are set based
on hardware specifications for each specific FlexCAN instance.
This property addition ensures proper resource allocation and
prevents buffer overflow issues in FlexCAN driver implementations.
Signed-off-by: William Tang <william.tang@nxp.com>
The /soc node is a simple-bus node and not an interrupt provider. Leaving
the #interrupt-cells property produces misleading Device Tree build
warnings:
Warning (interrupt_provider): /soc: '#interrupt-cells' found, but node is
not an interrupt provider <stdout>: Warning (interrupt_map): Failed
prerequisite 'interrupt_provider'.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Supporting irqsteer using NXP HAL becomes increasingly harder with new
SoCs.
For example now there are two incompatible HAL drivers for IRQ steer
(mcux-sdk-ng/drivers/irqsteer and mcux-sdk-ng/drivers/irqsteer_1).
In order to avoid overcomplicating code and better scaling code for
newer SoCs just drop using the NXP HAL and implement an IRQ Steer native
Zephyr driver
Use irqsteer node of imx943 as example.
New features:
- Support multiple irqsteer instances.
- Indroduce new properties(nxp,irq-offset, nxp,num-irqs).
Signed-off-by: Biwen Li <biwen.li@nxp.com>
This adds priority attribute to irqsteer in order to
support multi level interrupts.
We need to make this change atomic so that we don't break
the build.
So, we introduce a new property named 'priority' to
`interrupt-cells` and we increase the number of cells.
Then we update all instances of interrupts
using irqsteer (for imx95, imx8m, imx8qm, imx8qxp and also
update the overlay(imx8mp_evk_mimx8ml8_adsp) for tests.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
1. Enable SAR ADC support for nxp mcxe31x platform.
2. Enable SAR ADC support for nxp frdm_mcxe31b board.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Zephyr's current ADC API only supports 32 logical channels,
which is inadequate for SAR ADCs on certain SoCs. For instance,
the ADC on the MCXE31B has 64 hardware channels. The previous
implementation used a one-to-one mapping between logical and
hardware channels. In the new SAR ADC driver version, we bind
hardware channels to logical channels via the zephyr,input-positive
property, enabling us to access any channel.
Currently, only imx93 uses this ADC. To maintain the bisectability
of Zephyr commits, in this commit we will also modify the imx93-related
files, inlcuding:
1. Update the clock_control_mcux_ccm_rev2.c to use the new Kconfig
option 'CONFIG_ADC_NXP_SAR_ADC'.
2. Add properties to the imx93_evk_mimx9352_m33.overlay of the adc_api
testcase.
Now the sar adc is native driver, so, remove
CONFIG_MCUX_COMPONENT_driver.sar_adc from the glue cmake.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
S32K566 is a member of the S32K5 family which expands
s32k3 series to higher performance and larger memory.
Zephyr port for S32K5 will support cortex-M7 and cortex-R52
After reset, swt_startup is enabled and starts running,
disable it using the watchdog hook.
Signed-off-by: Ha Duong Quang <ha.duongquang@nxp.com>
Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
1. We shall set the proper clock source for lpcmp.
2. The property '#io-channel-cells' is currently
not needed for LPCMP.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
We are planning to implement a new LPCMP driver based on the
comparator API and deprecate the current sensor-based driver.
We would like to use the nxp,lpcmp binding for the new
comparator-based driver implementation. To avoid naming conflicts,
we are renaming the current sensor binding to nxp,sensor-lpcmp.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Spec - Section 2.3.8
> If the property is defined with an <empty> value, it specifies that
the parent and child address space is identical, and no address
translation is required.
Spec - Table 2.3
> <empty>: Value is empty. Used for conveying true-false information,
when the presence or absence of the property itself is sufficiently
descriptive.
`ranges = <>;` should be interpreted as `<prop-encoded-array>` with
empty array, when processing the child the ranges should be used and
given it is and empty array we will fail to map and behaviour
is undefined by the dts spec!
Hence IMO `ranges;` is the correct syntax here. This leaves no space
for uncertainty and undefined behaviour by tools and
user interpretation.
Signed-off-by: Kyle Bonnici <kylebonnici@hotmail.com>
Add new configuration item color_coding in the structure
mipi_dbi_config and in mipi-dbi-device binding property.
The color coding is defined by MIPI Alliance Standard for
Display Bus Interface v2.0, which is required by some display
controllers and device.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
add initial version of devicetree for amebad SOC.
amebad devicetree file is main platform dtsi file, which should
be included from board dts (e.g rtl872xd_evb.dts)
Signed-off-by: zjian zhang <zjian_zhang@realsil.com.cn>
The `renesas,ra-adc` compatible was replaced by `renesas,ra-adc12`,
at #95710 but one ADC devicetree node was not updated accordingly.
This commit updates the missing node to use the correct
`renesas,ra-adc12` compatible.
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Tested:
Verified that reading and writing data to the PSRAM
with MCU's FlexSPI controller in Quad Mode, works as
expected.
Signed-off-by: Nikhil Namjoshi <nikhilnamjoshi@google.com>
Enabled modes:
idle: SLEEP
suspend: DEEP-SLEEP
standby: POWER-DOWN with CPU retention
OS Time Base: OSTIMER with 32K clock source
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
- Update the driver to support the PSE84 device
- Update to new peripheral clock allocation scheme
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Add devicetree bindings for the FocalTech FT9001 SoC:
- Clock controller
- Reset controller
- UART
These bindings are required by the SoC and drivers added in subsequent
commits. Headers are placed under include/zephyr/dt-bindings/.
Signed-off-by: Robert Cheng <robert.cheng@focaltech-electronics.com>
This commit enables use of FTFC flash controller.
Together with DT changes it adds support for FTFC into soc_flash_mcux.c
driver.
Signed-off-by: Petr Buchta <petr.buchta@nxp.com>
The driver was unconditionally setting hal_dev->cs_pin_id to the target
number, which activates hardware CS lines even when GPIO-based chip
select (cs-gpios) is used. This caused issues when using hardware CS
via pinctrl with reg > 0.
Also update the binding documentation to clarify the interaction between
cs-gpios and hardware CS via pinctrl.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
