The DMA_MCUX_EDMA_V5 configuration option has been removed and replaced
with DMA_MCUX_EDMA_V4, as both versions share the same register layout
and can use the same driver implementation.
Key changes:
- Remove CONFIG_DMA_MCUX_EDMA_V5 Kconfig option
- Replace DMA_MCUX_EDMA_V5 conditionals with DMA_MCUX_EDMA_V4
- Remove DMAx_Type typedef, use DMA_Type directly
- Update EDMA_HW_TCD macros for V4 to use HAL-provided accessor macros
- Add DMA_MCUX_EDMA_DMAMUX Kconfig option to control DMAMUX support
based on device tree property
- Update device tree binding to add has-dmamux property
- Update HAL driver selection to use DMA_MCUX_EDMA_DMAMUX instead of
DMA_MCUX_EDMA for DMAMUX component
- Add SOC_SERIES_MCXE31X to DMA_MCUX_TEST_SLOT_START configuration
- Calculate DMA_TCD_ALIGN_SIZE from edma_tcd_t structure size
Signed-off-by: Qiang Zhang <qiang.zhang_6@nxp.com>
Include package-level I/O mapping for I2C pins
in psoc4100tp.64-tqfp.dtsi
Signed-off-by: Manojkumar Konisetty <manoj@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
The reg property on the NPU node indicated a base address of 0x580C0000 and
size of 4 KiB, neither of which are correct (in fact, this base address is
the one of the OTGPHYC2).
Set the reg property to the correct values: the NPU instance is mapped at
0x580E0000 and occupies 128 KiB of address space.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add device tree node for ESP32-C6 SoC ROM at 0x40000000.
This 320KB ROM contains libc and utility functions used by
the application. PMP protection is configured separately
via PMP_SOC_REGION_DEFINE in pmp_regions.c.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
rework litex gpio driver.
It is now also supported to change direction.
now uses the reg names to detect if what modes the gpio
controller supports.
use the reg names directly from litex.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
add test for DT_ANY_INST_REG_HAS_NAME_STATUS_OKAY
and DT_ALL_INST_REG_HAS_NAME_STATUS_OKAY macros.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add PWM driver support for Renesas RZ/A2M
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
- Update clk-source to 1 for all flexcan instances because
we need to use sysclk as PE clock source and reduce customer's
confused when configuring flexcan clock
If user use a fast external osc and want to choose another choice,
user can change it in overlay files
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Add a "run-mode" devicetree property to the NXP i.MX GPT counter
driver to control counter behavior on compare events.
The property supports two modes:
- "restart": Counter resets to 0 when reaching Compare Channel 1 value
- "free-run": Counter continues counting without reset
This change makes the GPT run mode configurable per device instance
instead of being hardcoded. The driver now derives the enableFreeRun
setting from devicetree, defaulting to "restart" mode.
This update aligns the GPT driver configuration approach with the
NXP LPTMR counter driver, which also uses devicetree properties
for runtime behavior configuration.
This provides consistency across NXP counter drivers in how hardware
behavior is controlled through devicetree.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Set default values for BLE HCI buffer configuration that match
the ESP32 controller requirements:
- BT_BUF_ACL_RX_COUNT=24: Match controller's ACL buffer count
- BT_BUF_EVT_RX_COUNT=30: Match controller's event buffer count
Enable BT HCI node in device tree for all ESP32 SoCs that
support BLE.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Enables hardware RX timestamping for the STM32 FDCAN driver by
leveraging the M_CAN timestamping interface.
Introduces a new `timestamp-counter` property in the device tree binding.
If `CONFIG_CAN_RX_TIMESTAMP` is enabled and this property is defined,
the driver configures the M_CAN Timestamp Select to use the
external timestamp counter value.
This allows linking a Zephyr Counter device to the FDCAN instance to
provide precise packet timing.
Signed-off-by: Igor Knippenberg <knippenberg@filics.eu>
This driver is currently only supporting the polling-mode read_and_decode
APIs (both blocking and non-blocking).
The driver implements a chip_api structure which has to be used to
provide device specific callbacks. The only lsm6dsvxxx family device
currently supported is lsm6dsv320x.
More information about LSM6DSV16X:
https://www.st.com/resource/en/datasheet/lsm6dsv320x.pdf
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The Device Tree property names that are common to lsm6dsv16x and
lsm6dsv32x drivers are now prefixed with LSM6DSVXXX_ (and not
LSM6DSV16X_) just for the sake of clarity.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
- Adds devicetree node of watchdog in same5xd5x family
- Adds the binding yaml for g1 driver of watchdog
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
Add ADC driver support for Renesas RZ/A2M
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Add Support for MAX30210, a low-power,
high-accuracy digital temperature sensor
operating from a 1.7 V to 2.0 V supply.
Signed-off-by: Francis Roi Manabat <francisroi.manabat@analog.com>
All series set the "zephyr,entropy" chosen to the internal TRNG by default
inside their root DTSI except STM32N6 and STM32WB0.
Align these two series with others by declaring "/chosen/zephyr,entropy" in
their root DTSI as well.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add initial support for the Allwinner H3 SoC, commonly
found in development boards like the Orange Pi series.
This commit introduces the intial SoC support files:
- Basic Kconfig configuration and SoC definition
- MMU region setup for memory management
- SoC-specific headers and device tree source include
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Enable support for configuring and enabling the external timestamp counter
of the NXP LPC MCAN.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add support for configuring and enabling the internal timestamp counter of
the Bosch M_CAN IP core.
Frontend drivers can overwrite this configuration for using a SoC-specific,
external timestamp counter.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Remove old resolutions property from the st,stm32-adc binding and from all
ADC nodes of all STM32 dtsi since it is no longer used.
Also remove some now unnecessary includes from the dtsi.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a new st,adc-resolutions property for STM32 ADC. This property takes
a simple array of the supported resolutions. Goal is to replace to previous
resolutions property.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fix typos in property descriptions in the NRFS SWEXT power domain
binding.
No functional change.
Signed-off-by: Gaetan Perrot <gaetan.perrot@spacecubics.com>
Adds bindings for communicating with the MCTP protocol over I3C with IBI
for signaling.
Notably I3C currently requires devices on the bus be struct device's the
way the Nuvoton driver is written and the API is written. So we create a
little glue driver (mctp_i3c_endpoint) to allow us to later bind a aptly
named mctp_i3c_controller MCTP binding.
On the target side the only usable driver for target mode is Nuvoton's.
Nuvoton's driver only implements the optional buffer read/write
callbacks rather than the read/write byte at a time callbacks. This is
actually probably for the better but it does mean this binding requires
those optional target mode functions.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
so that time-consuming I/O takes place in the background. This is
especially important when writing to multiple long LED strips.
This commit mostly mirrors what was done in the pl022 driver and the
rpi_pico_pio_spi driver, including the needed DT configuration. DMA will be
used if `CONFIG_DMA` is enabled and proper `tx` channel is defined in the
DT.
The DT overlay I used when testing:
```
&pio0 {
status = "okay";
pio-ws2812 {
compatible = "worldsemi,ws2812-rpi_pico-pio";
status = "okay";
pinctrl-0 = <&ws2812_pio0_default>;
pinctrl-names = "default";
bit-waveform = <3>, <3>, <4>;
/* This device has no tx channel configured so DMA will NOT
* be used. */
ws2812_1: ws2812_1 {
status = "okay";
gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
chain-length = <1>;
color-mapping = <LED_COLOR_ID_GREEN
LED_COLOR_ID_RED
LED_COLOR_ID_BLUE>;
reset-delay = <280>;
frequency = <800000>;
};
/* This device has proper tx channel configured so DMA will
* be used. */
ws2812_2: ws2812_2 {
status = "okay";
gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
chain-length = <64>;
color-mapping = <LED_COLOR_ID_RED
LED_COLOR_ID_GREEN
LED_COLOR_ID_BLUE>;
reset-delay = <280>;
frequency = <800000>;
dmas = <&dma 1 0 0>;
/* DMA slot will be
* determined by the driver so what's in here
* doesn't matter. */
dma-names = "tx";
};
};
};
&dma {
status = "okay";
};
```
Signed-off-by: Terry Geng <terry@terriex.com>
Update the system clock device tree definitions for the Infineon
PSoC4100TP series.
Refactor the peripheral divider nodes in `system_clocks.dtsi` to
align with the hardware specifications. This includes renaming nodes
and updating group associations for correct clock configuration.
Update `infineon,peri-div.yaml` binding to support the changes.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Update all Infineon PSoC4100TP device tree nodes to use current
binding naming convention by removing the 'cat1-' prefix
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Add the memory-regions property to mac in stm32h7rs.dtsi,
same as in stm32h7.dtsi, and set sram2 as default. Also add
the #memory-region-cells to sram2 and sram1 nodes.
Override the sram2 as default with sram1 in stm32h7s3.dtsi and
stm32h7s3.dtsi since sram2 is disabled per default.
Add the same checks as for h7 series to mpu_regions.c and sections.c.
Signed-off-by: Benjamin Klaric <benjamin.klaric01@gmail.com>
Use the memory-regions property in stm32h7.dtsi to explicitly locate
ethernet buffer and descriptor to an sram region. Set sram2 as default
and override with sram3 when available, in soc level .dtsi files.
Add #memory-region-cells to sram2 and sram3 nodes in specific .dtsi
files in dts/arm/st/h7, since it is needed by the memory-regions
property.
Add a check for memory-regions before the check and definition of the
sram_eth_node in mpu_regions.c and sections.ld.
Signed-off-by: Benjamin Klaric <benjamin.klaric01@gmail.com>
Add the compatible for h5 series for ethernet. The h5 series needs
it own because the memory-regions property isn't currently supported
by the implementation.
Add the h5 compatible to stm32h563.dtsi, in mac node.
Adjust the description in h7 compatible to remove the mention of h5
series, as now h5 series has it's own.
Signed-off-by: Benjamin Klaric <benjamin.klaric01@gmail.com>
Add support for configuring the SysTick clock source via devicetree
using a new `clock-source` property. This allows selecting between
the external reference clock (0) and the processor clock (1).
Previously, the driver always set the CLKSOURCE bit, forcing the use
of the processor clock. This change introduces a helper function
`systick_ctrl_clksource_flag_from_dt()` that reads the devicetree
property and returns the appropriate CTRL register flag.
The CTRL register is now programmed deterministically using direct
assignment instead of `|=` to ensure the CLKSOURCE bit is properly
cleared when switching to external clock, preventing potential
interrupt storms when CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC reflects
the external clock rate.
If the property is absent, the driver defaults to legacy behavior
(processor clock).
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
