The EFM32HG (Series 0) WDOG has no IRQ support, no window mode
and no reset-disable bit.
Guard the logic with HAL feature macros and use `IF_ENABLED` with
`DT_INST_IRQ_HAS_IDX` for conditional IRQ setup.
Add the `wdog0` node to the EFM32HG device tree.
Signed-off-by: Patryk Koscik <pkoscik@antmicro.com>
Add support for software resets in case no reset GPIO can be provided.
Add a mailbox write to prevent hibernation during bringup because
we can no longer rely on a hardware reset to make sure the device is
not hibernating.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
Split the generic cirrus,cs40l5x compatible into device-specific
variants. Update the driver and Kconfig accordingly. Update the
CRD40L50 demonstration board's compatible to cirrus,cs40l50. Move
the device ID from the data struct to the config struct. Move uses
of DT_ANY_INST_HAS_PROP_STATUS_OKAY() and similar macros from the
device driver to Kconfig to support new DT_DRV_COMPAT usage in the
driver.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
Introduce a PECI transport driver that operates over the eSPI bus,
enabling platforms without a native PECI controller to communicate
with the host CPU via an embedded controller.
This driver:
- Implements the PECI transaction layer on top of eSPI OOB channel
- Serializes PECI transactions to ensure protocol correctness
- Integrates with the existing PECI core infrastructure
- Allows PECI consumers (e.g. DTT, thermal, power management) to remain
transport-agnostic
A corresponding devicetree binding enables PECI-over-eSPI by defining
a PECI child node under the eSPI controller node.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Add an invert-direction boolean DT property that negates the axis value
reported by the event worker. This handles boards where the physical
encoder orientation produces a direction opposite to what the quadrature
state machine reports without swapping the A/B GPIO wires.
Signed-off-by: Andrew Yong <me@ndoo.sg>
Add a Supervisor-mode board variant for the QEMU RISC-V 64-bit virt
machine so twister exercises S-mode in CI.
Configure board.cmake to append s=on,u=on,pmp=on,priv_spec=v1.12.0,
sv39=on when CONFIG_RISCV_S_MODE is set, using string(APPEND) consistent
with the CONFIG_RISCV_PMP flag handling.
Three flags are required for compatibility with the rv64i bare CPU in
QEMU 10 (shipped with the Zephyr SDK):
- sv39=on instead of mmu=on: QEMU 10 separates MMU hardware presence
from the satp addressing mode; without an explicit mode QEMU defaults
to bare and virtual addressing is disabled.
- pmp=on: the rv64i bare CPU has no PMP by default; reset.S writes PMP
CSRs unconditionally, causing an illegal-instruction trap before UART
is initialised if PMP support is absent.
- zicntr=on: QEMU 10 separates Zicntr from the base I extension; without
it csrr time traps with mcause=2 in the M-mode SBI timer handler.
Set riscv,privilege-modes = "m", "s", "u" on all cpu nodes in the
S-mode devicetree overlay so all harts correctly describe Supervisor-mode
support on SMP systems. Simplify the privilege-modes binding wording to
avoid implying that only M-mode is assumed when the property is absent.
Exclude tests incompatible with S-mode: semihosting (requires M-mode
firmware), shared-interrupt tests (only one software-triggerable IRQ in
S-mode), and the RISC-V ISR table tests (timer IRQ already claimed).
Signed-off-by: Alexios Lyrakis <alexios.lyrakis@gmail.com>
Introduce CONFIG_RISCV_S_MODE to select Supervisor-mode execution.
Add depends on !RISCV_S_MODE to RISCV_PMP since PMP CSRs are
inaccessible from S-mode.
Add an M-mode SBI shim (reset.S + sbi.S) that configures exception
delegation, PMP, and counter access before dropping to S-mode via mret.
The shim handles SBI_SET_TIMER ecalls from S-mode and forwards MTIP to
STIP so the supervisor timer driver works without a full SBI firmware.
Introduce privilege-level abstractions in isr.S (RV_CAUSE, RV_EPC,
RV_STATUS, RV_TVAL, etc.) and update all runtime code that previously
accessed M-mode-only CSRs (mcause, mtval, mstatus, mie, mip) to use the
S-mode equivalents when CONFIG_RISCV_S_MODE is set.
ARCH_EXCEPT in kernel context uses ebreak (cause=3, Breakpoint) instead
of a direct z_riscv_fatal_error() call. In S-mode, ecall (cause=9) is
kept in M-mode for SBI and never reaches the S-mode exception handler;
a direct call with NULL esf caused the stack unwinder to crash into an
infinite fault loop. ebreak is delegated to S-mode by our medeleg
configuration; isr.S treats ebreak with t0=RV_ECALL_RUNTIME_EXCEPT the
same way M-mode treats ecall-based ARCH_EXCEPT.
Signed-off-by: Alexios Lyrakis <alexios.lyrakis@gmail.com>
The new hardware supports fifo mode for all i2c channels. This commit
adds support for fifo mode across all i2c channels.
Additionally, the compilation fails when the `I2C_IT51XXX_FIFO_MODE`
option is disabled because the isr function is behind this option.
This change also resolves this issue.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Add support for the SkyStar-GD32F407VET6 board:
- Board documentation describing hardware features and usage
- Pin control for USART0 and PWM
- DTS defining GPIO, LEDs, keys, and PWM
- YAML metadata for board ID, memory, and vendor
- Default defconfig enabling MPU, console, UART, and GPIO
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
Co-authored-by: RUANG (James Roy) <longjinyii@outlook.com>
Remove unnecessary #address-cells and #size-cells from lpcomp0 nodes
as they have no addressable child resources.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Remove unnecessary #address-cells and #size-cells from lpcomp0 nodes
as they have no addressable child resources.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This patch applies a software reset command under the condition that no
gpio reset pin is assigned and the new introduced boolean softreset-on
had been set for the device in the device tree or overlay.
Signed-off-by: Chris Ruehl <chris@gtsys.com.hk>
Update the RT7xx EHCI nodes to use clkctl4 clock specifiers and
describe the controller and PHY clock rates in devicetree.
Remove the obsolete usbclk fixed-clock node because the USB clocks
are now provided through clkctl4.
This provides the clock information used by the EHCI driver on
RT7xx.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Correct the STM32WBA2x internal flash write block size, sector size
and sector erase time configuration data that differ from STM32WBA5x
and STM32WBA6x. Configuration data can be found in STM32WBA2xxx
datasheet DS15003 [1].
Link: https://www.st.com/resource/en/datasheet/stm32wba25ce.pdf [1]
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add PWM driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Pulse width modulation output
- Period and pulse width configuration
- Polarity inversion
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add empty ranges property to STM SoCs internal flash controller
that were missing when ranges properties were added to internal
flash device nodes in commit 876552f92c ("dts: arm: st: add address
ranges info in SoCs internal flash nodes").
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Describe RT700 USDHC reset lines with the SoC reset
controller so the driver can acquire and release reset
through the common reset API.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
add offset-base for nxp,rstctl.yaml to support SoCs
that encode reset IDs in a single global namespace
across multiple RSTCTL instances.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add support for the i2c .recover_bus api in Infineon's i2c_pdl
driver. This uses the functions defined in i2c_bitbang.c to cause a
release of an improperly held sda line.
Additionally, changes are made to the driver's relevant Kconfig
and i2c binding .yaml files. This adds definitions for the sda and scl
bins for recovery purposes. The .recover_bus api is set to depend on the
"scl_gpios" and "sda_gpios" variables being set up in devicetree.
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
Add the necessary USB node for the max32666.dtsi and enable the device on
the MAX32666EVKIT which exposes a USB connector that works as expected.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
MCXL25x cpu1 (cm0) core build is not supported.
Move aon_peripherals to separate dtsi file to allow loading it
independently from main domain peripherals. Move cpu1 definition
to cm0 specific files. Add aon_sram range for cm33 core.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Add DTS support for the two mikroBUS connectors on the sama7g54-ek board.
This adds:
- mikroBUS 1 and mikroBUS 2 header mappings
- board wiring for the shared mikroBUS I2C and SPI interfaces
- board aliases for mikroBUS header, I2C, and SPI use
Tested with:
- MIKROE ETH Click
- MIKROE Weather Click
- MIKROE Ambient 2 Click
Signed-off-by: Balaji Vasudevan <balaji.vasudevan@microchip.com>
Add supports for XIAO ESP32C5, a compact development board based on the
ESP32-C5 SoC.
Assisted-by: Cursor:composer-2
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
- Add header for clock defintions used by the devicetree.
- Add clock node.
- In soc.c, parse clock node config from the devicetree and apply them.
Signed-off-by: Scott Laboe <scottyl2.718@gmail.com>
