Remove INPUTMUX interrupt assignments for PINT and GPIO peripherals.
Remove gpio0 DT node.
As the GPIO peripherals can be secured on the mimxrt798s, accesses from
the cm33_cpu0 and hifi4 are mutually exclusive, so the GPIO0 will stay
enabled in the cm33_cpu0 domain.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
This property allows a user to specify the operation of a
pin in sleep mode.
By default, pins are configured to be output low in sleep mode.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The nPM1300 datasheet featured wrong soft start current values which
were also used in the DTS bindings for its regulator driver. This fixes
the values aligning them with the next release of the document.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Introduce the ACE 4.0 architecture, along with support for the NVL and
NVL-S platforms within the Intel ADSP framework in the Zephyr project.
This update includes:
- Addition of ACE 4.0 architecture configurations in Kconfig and
Kconfig.intel_adsp.
- Inclusion of device tree source files for NVL and NVL-S platforms,
defining CPU, memory, and peripheral configurations.
- Updates to driver files to support ACE 4.0 specific features,
including DMIC and SSP configurations.
- Introduction of new header files for ACE 4.0, detailing boot,
interrupt, IPC, power, and shim functionalities.
- Modifications to the CMakeLists.txt to include ACE 4.0 MMU support.
- Addition of default configurations for NVL and NVL-S platforms in
Kconfig.defconfig.ace40.
The NVL and NVL-S platforms are part of the Nova Lake series, targeting
advanced audio processing capabilities. ACE 4.0 introduces enhanced DSP
capabilities and advanced power management features, improving audio
stream handling and synchronization compared to ACE 3.0.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit to initial support dts SoC layer on RX261
Signed-off-by: Hau Ho <hau.ho.xc@bp.renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Use HAL functions, which also wait for reset to complete.
Remove unused register size and active-low DT props.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
1.Add dts bindings nxp,lpit-channel.yaml and nxp,lpit.yaml
2.Provide counter driver based on lpit driver from NXP mcux-sdk-ng
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
emw clk designed on RT1180 can be chosen by CLKCTRL register,
add code to get sel from dts and configure it in driver.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Adds common and SoC-specific .dtsi files for the Microchip
SAM D5x/E5x family. These files define core peripherals,
address maps, and interrupt controller structure shared
across the SAM D5x/E5x variants.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
Updated the LPADC instance numbers in the
device tree to line up with the indexing
done in the RM.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Defines a VDAC node for xg23 and xg24 parts, which are all
compatible with the silabs,vdac binding.
Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
Defines bindings that are compatible with Silabs VDAC.
Reference your part's design book when configuring
values for the properties.
Signed-off-by: Bastien Beauchamp <bastien.beauchamp@silabs.com>
Extended clock control driver to support new DVFS service
from IronSide secure domain. Added new compatible nrf-iron-hsfll-local
which can be used to enable new DVFS service support in local
domain.
Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
Added the gpio driver for EFR series 2 devices.
The SILABS_SISDK_GPIO symbol is added to enable
support for the new GPIO driver.
The SOC_GECKO_GPIO symbol is retained for now to
maintain compatibility with existing drivers and
will be removed in a subsequent commit.
Signed-off-by: S Mohamed Fiaz <fiaz.mohamed@silabs.com>
Add new feature flags to gpiote node.
Include pinctrl. Pins used by GPIOTE0 on nrf54h20/cpurad require CTRLSEL
configuration. Pins are listed using pinctrl and parsed by nrf-regtool
to prepare UICR configuration.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add support for configuring the maximum TX power for STA and AP modes using
a Device Tree property (`max-tx-power`). If unspecified, the default value
is set to 31 dBm.
Signed-off-by: Arunmani Alagarsamy <arunmani.a@silabs.com>
The flash M1K driver supports read (up to 1K), write (1K), and
erase (4K) operations, which can be accessed via DLM.
Accessible flash regions include internal e-Flash or external SPI
flash via FSCE# or FSCE1#.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add initial support for the Cortex-M52 Core which is an implementation
of the Armv8.1-M mainline architecture.
The support is based on the Cortex-M55 support that already exists in
Zephyr.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Update the bit offset of bit VCC_STS in the BKUP_STS register.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
