Add initial board support for the Armfly STM32H743XIH6 board.
This includes board metadata, devicetree, and documentation.
Add runner configuration for flashing and debugging.
Signed-off-by: Zhaoming Li <lizhaoming634@gmail.com>
Add a board variant for running the FVP_Base_RevC-2xAEMvA simulator
in AArch32 execution state, using the SOC_V8A_AARCH32 SoC variant
introduced earlier. The FVP is configured with cluster0.has_aarch64=0
to disable AArch64 capability at all exception levels, forcing the
cores to execute exclusively in the AArch32 state.
Also, add dts/arm/armv8-a.dtsi as a base dtsi for Armv8-A AArch32
platforms.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add support for the Cortex-A32 processor. The Cortex-A32 processor
is built on the ARMv8-A architecture and supports only the AArch32
execution state.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add hardware CRC32 peripheral node to the Ambiq Apollo510 device
tree include file. The node is disabled by default and placed in
the crypto power domain.
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Add devicetree binding for the Ambiq hardware CRC32 module.
The binding describes a hardware-based CRC32 calculation peripheral
and requires a reg property.
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Wires interrupt routing for the ElemRV-N board: configures the
PLIC with 7 interrupt sources (riscv,ndev = <7>), routes GPIO0 to
PLIC IRQ 1 (priority 1) and UART0 to PLIC IRQ 5 (priority 1) in
the platform DTSI.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Adds a sifive,plic-1.0.0 PLIC node to the Nitrogen platform DTSI,
mapped at 0xf0800000 (64 MiB region), connected to
HLIC M-mode (IRQ 11) and S-mode (IRQ 9) external interrupt lines,
with up to 7 priority levels.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Move RMII data plane pin selection to the pinctrl-0 property using
the RMII_* macros from the SoC pinctrl header. The pads use dedicated
EMAC IOMUX, so the driver reads the (slot, GPIO) pairs and routes them
directly instead of through pinctrl_apply_state(). Update the esp32
ethernet kit board to use the new rmii_default group.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The NXP SCTimer's outInitState field defines the output levels applied at
initialization, before any PWM channel is configured. Needed for active
low loads to not flicker at startup
Signed-off-by: Johan Eklund <Johan@meck.se>
Nordic's nPM10 Series PMIC LED driver and Devicetree bindings.
LED driver outputs on nPM10 devices are multiplexed with GPIOs.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
On MCXW7x the clock controller does not auto-enable peripheral gates;
each driver enables its clock in init via device_is_ready() and
clock_control_on(), as already done by lpuart, lpi2c and gpio. Bring the
NXP CRC driver in line with that model: enable the CRC clock through the
clock-control framework when the node provides a "clocks" property
(guarded by COND_CODE_1, so MCXN/LPC parts without one are unchanged),
and add the clocks property to the MCXW70/MCXW71/MCXW72 CRC nodes.
The MCUX HAL CRC_Init() also ungates the clock, so the peripheral was
already functional; this expresses the clock dependency in devicetree
and lets the clock-control framework track it.
Tested with tests/subsys/crc on frdm_mcxw70 and frdm_mcxw71:
pass = 14, fail = 0.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The CRC node for MCXW70AC was declared at offset 0x23000 (absolute
0x50023000), reusing the MCXW71/MCXW72 memory map. On MCXW70AC that
address belongs to the PKC peripheral; the CRC instance is actually at
0x50018000 (CRC_0). The node therefore pointed into the wrong
peripheral.
Because the base matches no entry in the HAL's CRC instance table,
CRC_GetInstance() returns an out-of-range index. With assertions enabled
this trips assert(instance < ARRAY_SIZE(s_crcBases)) and panics; with
assertions disabled it indexes past the instance tables and operates on
the wrong register region, which is the bus fault reported during
CRC_Init() once CRC hardware was enabled on the MCXW7x platforms.
Point the node at the correct CRC_0 base (0x50018000).
Validated on MCXW70AC hardware (FRDM-KW43) with tests/subsys/crc: the
suite panics at the first CRC operation before the fix and runs CRC
operations normally after it.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The DMIC backend streams PCM samples from a host file via host-libc I/O
helpers, supports a command-line override for the input file path, is
documented in the native_sim board guide, and adds dmic to the supported
peripherals in native_sim.yaml.
Assisted-by: GitHub Copilot:GPT-5.4
Signed-off-by: Tomas Barak <tomas.barak@nxp.com>
Update common AIA coordinator shared by IMSIC and direct mode to
initialize based on which APLIC mode is configured in DT.
Signed-off-by: Omar Naffaa <onaffaa@qti.qualcomm.com>
Add devicetree support for AMD ACP 7.X audio DSP:
- dts/xtensa/amd/acp_7_x.dtsi: SoC-level dtsi defining the host
DMA controller, 4-instance SoundWire DMA controller, SoundWire
DAI nodes, and interrupt controller node with ACP 7.X specific
register base addresses and channel counts
- boards/amd/acp_7_x_adsp/acp_7_x_adsp.dts: board-level DTS that
includes the SoC dtsi and selects the active DMA and DAI nodes
for the acp_7_x_adsp board target
Signed-off-by: Sneha Voona <sneha.voona@amd.com>
Sanitize wakeup-line, de-assert-time and de-deassert-time DT properties
values for st,stm32-uart* compatible devices using min/max DT properties
instead of providing an informative only range description in the
related DT bindings YAML file.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Use min/max properties to define the valid ranges for applicable
DT properties st,timeout and st,deadtime for st,stl32-lptim and
st,stm32-timers compatible devices. This change ensures out-of-bounds
values are better reported with build error trace message compared
to previous informative only description in the YAML file.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Sanitize ifrgap, transwin, hbitclkdiv DT properties values for
st,stm32-ucpd compatible devices using min/max DT properties instead
of providing an informative only range description in the related
DT bindings YAML file.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Sanitize alrm-exti-line DT property value for st,stm32-rtc compatible
devices using min/max DT properties instead of providing an informative
only range description in the related DT bindings YAML file.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Replace description of valid ranges with using min/max
properties in DT bindings YAML files for ST operational amplifiers.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Replace informative only description of valid ranges for DT properties
of ST related sensors with use of min/max properties that allows
build time sanity check of embedded values.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Replace informative description of valid ranges in ST clock drivers DT
bindings YAML files with use a min/max properties that are now checks
against at build time.
The DT properties ranges impacted above where previously not checked
by the related drivers implementation.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add "long press" reset and SHPHLD wake-up configurations to the nPM10
Series MFD driver's Devicetree properties.
Signed-off-by: Sergei Ovchinnikov <sergei.ovchinnikov@nordicsemi.no>
Add a board overlay and inputmux in devicetree, so the PWM
loopback test runs on FRDM-MCXA153.
The OUT side drives CT1_MAT0 on P2_4 (J1_6) with ctimer1 in
PWM mode, the IN side routes CT_INP15 from P2_5 (J1_10) into
CTIMER2 CAPTSEL[0] via INPUTMUX for ctimer2 capture.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Implement the Zephyr PWM capture API using the CTIMER
capture-clears-timer feature.
One capture channel is configured to fire an IRQ on the active
edge while ENCC/SELCC clears TC+PC on the opposite (or same) edge so
that CR latches the period or pulse width directly with no software
subtraction. The INPUTMUX is configured at driver init from a new
inputmux-connections DT property that lists <captsel-index, connection>
pairs.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add a Raspberry Pi framebuffer display driver for the
Broadcom BCM2711 SoC. The driver communicates with the
VideoCore firmware via the Broadcom VideoCore mailbox interface.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Rename the mspi0 node from spi@40020000 to mspi@40020000 to
match the actual bus type. Update the compatible string from
ambiq,mspi to ambiq,mspi-controller to align with the binding
name used by the driver. Add clock-frequency = <48000000> as
the default operating frequency.
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Add support for interrup driven UART for the numicro uart driver
targeting the nuvoton m48x line.
This is mostly copied from the uart_numaker driver with some changes.
Signed-off-by: Fiona Behrens <me@kloenk.dev>
Use the new scc driver in the uart for the m48x numicro soc.
This removes quite a lot of calls into the nuvoton BSP and replaces
them with functions using the clock driver.
Signed-off-by: Fiona Behrens <me@kloenk.dev>
Adds devicetree bindings for the Infineon HPPASS Comparator Slope
Generator MFD device. The HPPASS CSG MFD device provides the base address,
shared comparator interrupt definition, and number of slices for the HPPASS
CSG subsystem.
Updates the psc3 devicetree definitions to include the CSG and five
entries each for the per slice comparator and DAC.
Assisted-by: Github Copilot:claude-opus-4.7
Signed-off-by: John Batch <john.batch@infineon.com>
The existing hwinfo_mcux_syscon driver handles the 128-bit UID
read with no driver changes required
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
Added mistakenly during the SAI rework, the presence of this property
inhibits `child-binding` inheritance; as a result, these nodes don't
have the proper binding and attempting to use them causes a build
failure when the driver tries to obtain DT_PROP(synchronous).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
- Create a dummy codec stub driver for testing and development purposes.
- Implemented dummy functions to satisfy the audio codec sample
- Add an audio_codec node and alias to the native_sim.dts
- Add Kconfig option
- Create a dts binding for the dummy stub
Assisted-by: GitHub Copilot:GPT-5.4
Signed-off-by: Tomas Barak <tomas.barak@nxp.com>
Enable the Wakeup Controller (WUC) subsystem for MCXW7xx SoCs when the
WUU (Wakeup Unit) device tree node is enabled.
Drop the SoC-local mcxw7xx_set_wakeup() shim and the
NXP_ENABLE_WAKEUP_SIGNAL() override: LPTMR0 wakeup is now configured by
the LPTMR timer driver via wuc_enable_wakeup_source_dt(), and NBU
wakeup is configured by the common NBU init code from the new
"wakeup-ctrls" property.
Add test overlay for frdm_mcxw72 board to validate WUC API.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Allow nodes with compatible "nxp,nbu" to declare a "wakeup-ctrls"
property by including wuc-device.yaml in the binding, and consume it
from the common NBU init code via wuc_enable_wakeup_source_dt().
When the property is absent, the existing NXP_ENABLE_WAKEUP_SIGNAL()
fallback path is preserved, so no in-tree user changes behavior here.
A failure from wuc_enable_wakeup_source_dt() is now logged and
propagates as an early return, which previously would have been
silently swallowed.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
The WUU driver supports:
- External pin wakeup sources with configurable edge detection
(rising, falling, or any edge) and event types (interrupt, DMA, trigger)
- Internal module wakeup sources with interrupt and DMA event types
- Up to 32 external pins and 9 internal modules
- Recording and checking of triggered wakeup sources
- Integration with the WUC (Wakeup Controller) subsystem
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Add helpers for the SCMI Reset Domain Management protocol and a Zephyr
Reset Controller driver that utilizes these helpers.
The update introduces protocol helper functions, a new driver,
relevant Kconfig and CMake entries, and device tree bindings.
Signed-off-by: Grygorii Strashko <grygorii_strashko@epam.com>
Signed-off-by: Svitlana Drozd <svitlana_drozd@epam.com>
