Extends the SCMI shared memory structure to phandles,
allowing TX and RX channels to use different shared memory regions.
This is necessary for platforms like i.MX95, where TX and RX
notifications are mapped to different addresses.
RX channel is not mandatory and depends on the platform's support
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
The flash on the ch32v series starts at 0x8000000 and, depending on
the system configuration, is aliased to 0x0. When the ch32v003 support
was first submitted, `minichlink` would accept either the real or the
alised address, but became stricter sometime in the last two years.
Fix the base address in the ch32v00{3,6}.dtsi, change
`minichlink.py` to always use the flash address from the build
configuration, and remove the `--dt-flash=y` work-arounds from the
more recent board configurations.
Tested by building `hello_world` for `ch32v003evt`, `ch32v006evt`,
`bluepillplus_ch32v203`, `ch32v303vct6_evt`, and `ch32v307v_evt_r1`;
running `west -v flash` and checking the command uses `0x8000000`.
Signed-off-by: Michael Hope <michaelh@juju.nz>
- add clocks and resets to MCXA CRC nodes.
- crc_nxp: deassert in init if a dt reset is given.
On MCXA SoCs the CRC peripheral boots held in reset, so enabling its
clock is not enough. Deassert the reset during driver init.
- nxp,crc.yaml: include reset-device.yaml for the resets property.
- mcxa Kconfig.defconfig: enable CONFIG_RESET
when MRCC reset is present.
- clock_control_mcux_syscon: enable the CRC clock gate.
- mcxa344: fix reset controller compatible to nxp,mrcc-reset.
Tested on frdm_mcxa344, frdm_mcxa156, frdm_mcxa266.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
On MCXW23 the OS event timer is reserved as the low-power companion
to SysTick and could not be used as the kernel system timer:
selecting CONFIG_MCUX_OS_TIMER left CORTEX_M_SYSTICK enabled, which
fails to link (duplicate sys_clock_* symbols), and no OS-timer clock
rate was defined for it.
Disable CORTEX_M_SYSTICK by default when MCUX_OS_TIMER is selected
(as already done for MCUX_LPTMR_TIMER) so only one system timer is
active, and define the OS timer clock rate. The MCXW23 OS event
timer is clocked from the 32.768 kHz RTC oscillator: PMC
OSTIMERCLKSEL resets to 32.768 kHz and is left at reset, and the
HAL only enables (never reselects) the clock. The rate is taken from
a clk_32k fixed-clock devicetree node rather than a hardcoded Kconfig
literal: SYS_CLOCK_HW_CYCLES_PER_SEC = 32768 and
SYS_CLOCK_TICKS_PER_SEC = 1024 (exactly 32 cycles per tick), unlike
other NXP parts where the OS timer runs at 1 MHz.
Selecting OSTIMER trades timing precision (~1 ms tick, ~30 us
resolution) for low-power always-on operation, so SysTick stays the
default where fine-grained timing is needed.
The default SysTick configuration is unchanged: both defaults are
gated on MCUX_OS_TIMER, which is off by default. A before/after
defconfig diff on frdm_mcxw23 is byte-identical (OSTIMER resolves to
HZ=32768/TICKS=1024, SysTick to HZ=32000000/TICKS=10000).
Link: MCXW23 RM section 45.4.11.2.24 (PMC OS timer control register)
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Like in nrf54lm20, reserve last 1kB from RAM for FLPR hibernation
if FLPR is in use. Hibernation is the default and recommended sleep
mode. Align nordic-flpr snippet.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The Devicetree recommends "crypto" as a generic name. Use it for nodes
representing cryptographic accelerators on STM32: AES, CRYP and HASH.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add a system clock driver built on top of the NXP System Counter
(SYS_CTR) block, which provides a 56-bit free-running counter and two
compare frames capable of generating maskable interrupts.
The driver is a free-running counter paired with an absolute compare
register. Compare frame 0 is used for the system timer, leaving frame
1 available for other consumers. The instance is selected via the
zephyr,system-timer chosen property.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
extended-channels node property is required to enable interval mode
support for nRF7120.
Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
Add a nocache memory region to mimxrt685s/hifi4's DT
(adsp_data_nocache). Move adsp_text and adsp_data from non-cached views
to cached views. Add Kconfig variables and symbols to SoC's memory.h
describing that region. Enable nocache memory support. Modify SoC's
linker script to set up linking against that memory region and add
nocache section initialisation to soc.c.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
The E8 SoC includes an APSS (Cortex-A32) cluster whose peripherals
are routed through a GIC. Add the GIC interrupt definitions for these
peripherals, complementing the NVIC definitions added earlier, so the
same peripheral instances can be reached from either the RTSS (NVIC)
or APSS (GIC) cluster with the correct interrupt routing.
As with the NVIC interrupt files, ae822fa0e5597ls0_gic_irq.dtsi
composes and presents the GIC interrupt routing for that SoC's resources,
and a board building for the APSS (GIC) core includes it instead of the
_nvic_irq variant.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Move interrupt properties from common peripheral definitions to
separate interrupt controller-specific files. This enables support
for SoCs where the same peripheral is wired to different interrupt
controllers.
Ensemble SoCs contain both RTSS (Cortex-M55 with NVIC) and APSS
(Cortex-A32 with GIC) clusters sharing the same peripherals. The
shared peripherals have different interrupt numbers depending on
the interrupt controller that routes the interrupts to the
corresponding CPU cluster. Moreover, NVIC and GIC use incompatible
interrupt specifier formats: NVIC requires two cells <irq priority>
while GIC requires four cells <type irq flags priority>. A single
peripheral node cannot carry both formats simultaneously, making
controller-specific interrupt files necessary.
Just as a <soc>.dtsi currently composes and presents the information
about the mem/io resources available in an SoC to the board layer,
the interrupt file <soc>_nvic_irq.dtsi (or <soc>_gic_irq.dtsi, to be
introduced later) composes and presents the information about the
interrupt routing for those resources. The decision to use either
of these (NVIC/GIC) interrupt files is taken at the board level as
the target CPU is only known at that level.
This commit introduces NVIC interrupt definitions while maintaining
existing functionality for all RTSS boards. GIC support will be
added in a subsequent commit.
No functional changes to existing boards.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Some SoC series in the Ensemble family contain a Cortex-A32 cluster
residing in their Application Processor SubSystem (APSS). Add a
device tree include file describing this cluster's CPU, GIC and Arm
generic timer.
This is the APSS counterpart of the existing ensemble_rtss_he.dtsi
and ensemble_rtss_hp.dtsi cluster files: the cluster-specific core
details are kept separate from the SoC-level on-chip resources so a
board can compose them per CPU variant.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Rename the DSI connector gpio-nexus compatible used on STM32 board
and name it st,dsi-lcd-qsh-030-connector to match with other
names of connectors used within the Zephyr tree.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
While the bindings file is refering (via its filename and
compatible) to st,dcmi-camera-fpu-330zh, the compatible
st,stm32-dcmi-camera-fpu-330zh is being used on board
device-tree.
Fix this align with other connectors by having the name contain
the type of connector and kind of usage.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
- Add pclk-hb-disable DTS property to control PCLK toggling
during horizontal blank periods. Different camera receivers may
have different requirement on this configuration.
- Reorder initialization sequence to apply format settings after
the common initialization table. Different format may apply differnt
configurations and overwrite the default configurations.
- Change the input XCLK frequency from 6MHz to 24MHz. According to
the data sheet and software application note, the camera sensor
requires the clock to be within the range of 10~48 MHz and the
typical value is 24 MHz. It can work with 6MHz XCLK but the
performance is not ideal. For example it glitches with VGA resolution.
- Fix resolution-specific register tables for QCIF, CIF, and VGA modes
with corrected timing and gamma settings for OV7670. When the OV7670
driver was originally enabled with the camera receiver smartdma, only
the QVGA resolution is tested, since smartdma can only support this
resolution, the others are not tested.
- Fix comment typo: case 352 is CIF, not QCIF
- Fix array size bug in QVGA format selection
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Now that the SoC can configure the active-mode DCDC output voltage
from the SPC device tree node, raise the default MCXW7x BLE TX power
to its maximum of 10 dBm.
Add 10 to the NBU max-tx-power-support list (dropping the stale
"TODO: Add 10dbm support" comment) and bump the default
max-tx-power-dbm from 7 to 10. Reaching 10 dBm requires the DCDC
regulator in its 2.5V custom mode, so set
active-dcdc-output-microvolt to 2500000 on the SPC node. The build
time cross-check in soc_dcdc.c enforces this pairing.
This affects the MCXW71 and MCXW72 families that share this common
dtsi; boards may still override max-tx-power-dbm if a lower limit is
needed.
Tested with samples/bluetooth/peripheral on frdm_mcxw71 and
frdm_mcxw72.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
The MCXW7x active-mode DCDC regulator output voltage was previously
fixed by the power init path, which only ran when CONFIG_PM was
enabled. Some use cases (notably reaching the highest BLE TX power
levels) require a specific DCDC output voltage to be applied
unconditionally at boot.
Add an optional "active-dcdc-output-microvolt" property to the
nxp,spc binding so the target voltage is described in the device
tree. The property is intentionally SoC-agnostic: legal values are
validated per-SoC in C rather than constrained by an enum in the
binding, since the shared compatible spans several SoC families with
different DCDC capabilities.
Implement the configuration in a new soc_dcdc.c that is compiled
unconditionally (independent of CONFIG_PM). nxp_mcxw7x_dcdc_init()
maps the configured microvolt value to the HAL DCDC level, sets the
VOUT2P5_SEL bit only for the 2.5V custom mode, and applies the change
with the active-mode voltage detectors saved, disabled and restored
around it. BUILD_ASSERTs reject values the DCDC cannot produce and
cross-check the configured voltage against the NBU max-tx-power-dbm
(10 dBm requires 2.5V, above 0 dBm requires at least 1.8V). When the
property is absent the routine compiles to a no-op and the DCDC
output voltage is left untouched.
Move the active-mode DCDC handling out of set_spc_configuration() in
power.c so the device-tree configured value is preserved and not
overwritten by the low-power init path. The logic is kept
self-contained so it can later be lifted into a dedicated SPC driver
without binding or device tree churn.
Tested with samples/bluetooth/peripheral on frdm_mcxw71,
frdm_mcxw72 and frdm_mcxw70 (the latter exercising the no-op path).
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Add a hwinfo backend that reports the reset cause on NXP MCUs that use
the MC_RGM (Reset Generation Module), such as the MCXE family, rather
than the Kinetis RCM/SIM blocks. The driver decodes the MC_RGM DES
(Destructive Event Status) and FES (Functional/External Reset Status)
registers into Zephyr RESET_* flags.
DES and FES status bits are write-1-to-clear, so
hwinfo_clear_reset_cause() writes back the latched bits it just read.
The backend binds to the existing "nxp,mc-rgm" compatible and reaches the
register block through the MC_RGM_Type CMSIS layout at the node's reg
address, so no fsl HAL component is required.
hwinfo_get_device_id is intentionally left as the weak -ENOSYS default:
the MCXE family exposes no per-die unique identifier (only SIUL2 MIDR
part identification), so reporting it as a device ID would be misleading.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
cpuppr is starting with a delay (>300 us) and cpuapp should not try
to communicate with cpuppr before it is up and running as any signal
set before cpuppr is ready is lost. One of available VPR events is
used to indicate cpuppr readiness.
Add property to nordic,vpr and nordic,nrf-vevif-task-tx bindings.
Add property to vpr and mailbox nodes. Reserve channel 15 for that.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Update the RT7xx EHCI host nodes to use clkctl4 clock specifiers
and describe the controller and PHY clock rates in devicetree.
This provides the clock information used by the host EHCI driver.
Signed-off-by: Aiden Hu <weiwei.hu@nxp.com>
New driver based on sysctrl acting as a watchdog.
After global software watchdog setup sysctrl will monitor
pings from particular local domain and reset SOC if ping
doesnt arrive before 6s timeout expires.
This software watchdog will be active only if local
domain will do wdt setup procedure.'
Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
Fix up the core MAX78000 devicetree includes to properly split M4 specific
pieces, define sram nodes correctly, and set up UART3 interrupts for either
core.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Add nxp,rcm-hwinfo reset-cause nodes to the KE1xZ and KE1xF SoC
devicetrees, and add the nxp,sim-uuid device-id compatible to the
KE1xF SIM node, so the existing NXP hwinfo RCM and SIM drivers are
available on FRDM-KE15Z, FRDM-KE16Z, FRDM-KE17Z, FRDM-KE17Z512 and
TWR-KE18F. KE1xZ has no unique-ID register, so only reset cause is
enabled there. Advertise hwinfo in each board's twister supported
list.
This extends existing NXP hwinfo driver coverage without changing the
driver implementation. Verified with tests/drivers/hwinfo: builds on
all five boards, and the suite passes on FRDM-KE17Z hardware (reset
cause tests pass, device id skipped).
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Drop the 'U' specifier in macro calls in the STM32U5 device tree files to
be consistent with other STM32 devicetree files.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Having separate file for SAI device complicates the reader/developper
comprehension of the overall device-tree, since there is already other
include mechanism into play. Remove stm32l4_sai.dtsi file and merge the
SAI node into corresponding files.
Signed-off-by: Raphaël Gallais-Pou <raphael.gallais-pou@foss.st.com>
According to the STM32 HAL documentation, the DQS port is
optional and can be disabled by passing port number 0.
Add 0 as a valid value for the st,dqs-port property to match
the documentation.
Signed-off-by: Kirill Shypachov <kshypachov@outlook.com>
use min-len/max-len for asserting the correct length of the
array, drop corresponding build asserts
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Following the introduction of the new stm32h5 dedicated pll-clock
compatible, update the compatible in device-trees.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
