Update STM32L4 PLL clock binding so that it can be used for all PLLs of
L4 and L5 series, removing the need for a specific PLLSAI binding.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Enable the SAR ADC peripheral on CY8CKIT-041S-MAX and
CY8CPROTO-041TP boards:
- Add ADC node to psoc4100smax.dtsi (SAR v2) and psoc4100tp.dtsi (SAR v3)
- Configure infineon,version property (2 for SMAX, 3 for TP)
- Configure clk-dst for peripheral clock routing
- 041S-MAX: PCLK_PASS0_CLOCK_SAR (0x12)
- 041TP: PCLK_PASS0_CLOCK_SAR (0xc)
- Reference peri_clk_div4 for ADC clock source
- Enable peri_clk_div4 in board common devicetree includes
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Co-authored-by: Deepika R <deepika@aerlync.com>
Co-authored-by: Sayooj K Karun <sayooj@aerlync.com>
Add driver for the Infineon SAR ADC peripheral with device tree
binding. The driver uses a generic compatible (infineon,sar-adc)
with an infineon,version property to differentiate IP block
revisions (v2, v3). Features include:
- Single-ended and differential channel configuration
- Configurable resolution (8-12 bits)
- Multiple voltage reference sources (internal, VDDA, VDDA/2, external)
- Channel reference validation against block-level vref-src
- Hardware compensation for SAR v2/v3 single-ended channel limitation
- Interrupt-driven conversion completion
- Integration with peripheral clock control
The driver includes a compile-time per-instance API structure to
correctly report reference voltage to the ADC framework for accurate
raw-to-millivolts conversion.
Tested on CY8CKIT-041S-MAX (SAR v2) and CY8CPROTO-041TP (SAR v3) boards.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Co-authored-by: Deepika R <deepika@aerlync.com>
Co-authored-by: Sayooj K Karun <sayooj@aerlync.com>
Initial generic driver for SPI-NAND devices that expose the ONFI
parameter page. Does not support advanced features such as continuous
reads, software ECC, or optional power down modes.
Configuration comes from devicetree in order to support other modules,
but is validated against the loaded ONFI data at boot.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The RV32 core does not implement RISC-V mtime, so add a new system
timer driver uses a peripheral timer for this functionality.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Moves some max32 devicetrees from arm to vendor to allow using them on
non-arm targets. This will make it possible to add support for the
secondary risc-v core that exists on these max32 variants.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
integrate the mdio driver area into the
ethernet driver area. mdio itself is defined as part
of the ethernet specification.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add a mailbox (Interprocessor FIFO) node to the RP2040 and RP2350 device
trees and a SIO block to hold this and any other future SIO peripherals.
This also includes an additional `zephyr,mbox-ipm` node that handles the
mailbox for core to core messaging.
The device is enabled for the Raspberry Pico Pi 2.
Signed-off-by: Ricardo Cañuelo Navarro <rcn@igalia.com>
This adds a driver for the interprocessor mailbox in the Raspberry Pi
Pico SoCs (RP2040/RP2350).
The SIO subsystem contains a set of low-latency peripherals, including a
pair of mailboxes (FIFOs) for inter-processor communication. One of the
FIFOs can only be written by core 0 and read by core 1, the other can
only be written by core 1 and read by core 0.
According to the datasheets [1] [2], the register interface is the
same in both SoCs and the only functional differences are that the
mailbox in the RP2040 is 8 entries deep vs 4 in the RP2350, and that the
RP2350 defines the same core-specific interrupt number, while the RP2040
defines two different IRQ numbers.
Tested on a Raspberry Pi Pico 2W (RP2350).
[1]: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf
[2]: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf
Signed-off-by: Ricardo Cañuelo Navarro <rcn@igalia.com>
Add missing fields in arm,stmesp binding and limit Coresight STM
frontend to SoCs which have the required hardware.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Until pygments/pygments#3021 is accepted and merged in upstream Pygments
we need to workaround some of the current limitations of the lexer with
overlay syntax. This fixes a doc build failure in main
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The STM32H56XXX family is available in 1 and 2 MB versions,
where
STM32H563 V I XXX
| | |
| | +- I: 2 MB flash
| | +- G: 1 MB flash
| |
| +- Pin count
|
+-- H562: without Ethernet
+-- H563: with Ethernet
All four options are available, but currently we only have
device trees for two of them.
Introduce two new device tree includes for the other
two combinations:
- stm32h562Xi.dtsi
- stm32h563Xg.dtsi
Signed-off-by: Stefan Gloor <stefan.gloor@siemens.com>
- Add ti,is-secure device tree property to indicate secure host entities
- Add is_secure field in device config
Signed-off-by: Dave Joseph <d-joseph@ti.com>
Adds the pinctrl node and encapsulates the port nodes within
the pinctrl node for pic32cm pl series of socs, and updates
the binding file
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
LTE modems typically support default PDP context (cid 0) which
is activated when network is attached.
Allow driver to choose whether this CID 0 is used by default, and
skip the whole APN state.
Some modems require PDP context to be defined by AT+CGDCONT=1 command
but do not necessary need the APN name.
Add both options as a Devicetree settings as an enum value so that
specific DTS bindings may change the default while allowing user
to override. Booleans with "default: true" would not work.
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
- Define the register region for controller and non-volatile
flash node which is 128Kb in size.
Signed-off-by: Manojkumar Konisetty <manoj@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Introduce the initial Device Tree Source Include (dtsi) files for the
Realtek RTL87x2G series SoCs.
The structure is organized as follows:
- rtl87x2g.dtsi: Contains the common definitions shared across all
part numbers in the RTL87x2G series.
- rtl8762gkh_gku.dtsi / rtl8762grh_gru.dtsi: Specific configuration
files to handle different flash sizes associated with these part
numbers.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Add two FIFO related properties for the st,stm32h7-spi bindings:
- Size of the FIFO
- Maximal size of the transfer when fifo-enable property is used
Also fill all dtsi files that require the new properties.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Improve the descriptions of the two STM32 FDCAN variants and add devicetree
node examples.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add device tree nodes for ns16550 compatible uart instances common
to all Socs in the ensemble family. Additional uart instances available
on specific SoCs will be added in the corresponding SoC specific dtsi
file.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add device tree include file for the Alif Ensemble E8 SoC
AE822FA0E5597LS0.
This dtsi defines resources specific to this SoC variant in
addition to the common peripheral definitions from ensemble_common.dtsi.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add device tree bindings for the Alif Semiconductor pin controller
and Ensemble SoC specific pin definitions.
The binding supports pin multiplexing via predefined macros that
encode port, pin, and alternate function into a 32-bit value.
Pad configuration (input enable, drive strength, slew rate, bias
control, etc.) is specified using standard pinctrl properties.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add devicetree binding for the Alif Semiconductor clock controller.
The clock controller manages peripheral clocks using registers spread
across multiple discontiguous regions (called clock modules in the
binding and driver).
Clock specifiers use a single cell containing an encoded clock ID
that packs module, register offset, clock enable information and
source clock information.
Co-authored-by: Manoj A Murudi <manoj.murudi@alifsemi.com>
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add fixed-clock nodes for some of the Ensemble family root clocks.
These clocks serve as input sources for peripheral clocks managed
by the clock controller.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
The Ensemble SoCs have a peripheral region at 0x1A000000 (8 MB)
that hosts peripherals such as pinmux and clock control registers.
This deviates from the standard Cortex-M memory map and requires
explicit MPU configuration with device memory attributes.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
The Alif Ensemble family of processors contains up to two
Cortex-M55 cores, each optimized for different use cases. One
configured to maximize power efficiency and the other to maximize
compute performance. These are called the High Efficiency Real Time
Subsystem (RTSS-HE) and the High Performance Real Time Subsystem
(RTSS-HP) respectively.
Add the device tree include files for these subsystems with their
CPU, MPU and TCM definitions.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
The child node does not need a compatible, the child properties are
inferred from the partent binding, plus this compatible is confusing the
documentation, which is failing with:
src/boards/microchip/pic32c/pic32cz_ca80_cult/doc/index.rst:36:
WARNING: 'dtcompatible' reference target not found:
microchip,pic32cz-ca-dpllchild [ref.dtcompatible]
1417
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
rng node is the default entropy source for nRF7120, so psa_rng should
be disabled by default.
Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
The TMP1075 binding defined conversion-rate and
consecutive-fault-measurements as optional properties with no
default values, causing build failures when they were omitted
from the devicetree node.
Add default values matching the hardware reset values from the
datasheet to fix the build failure.
Fixes#100362
Signed-off-by: Gokul Rajaram A <rajaramgokul25@gmail.com>
Add the missing `dtc` property to all Renesas RX SCI nodes. This property
provides a phandle reference to the DTC (Data Transfer Controller), which
allows the SCI driver to make use of DTC-assisted data transfers.
Signed-off-by: Y Huynh <y.huynh.xw@renesas.com>
Update the zhiantec,zfm-x0 binding description to include support for
Hi-Link HLK series capacitive fingerprint sensors (HLK-ZW3021,
HLK-ZW0623, HLK-ZW0642), which use the compatible ZFM protocol.
Signed-off-by: Siratul Islam <email@sirat.me>
