The "examples" section of the renesas,rcar-mfis-mbox.yaml was containing
an invalid dts fragment. Fix it.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This patch adds PM device support to the siwx91x ADC driver. It allows
the ADC to be reconfigured after waking from deep sleep. Without this
patch, the ADC peripheral fails to return valid values after the system
resumes from deep sleep.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
These SoCs are provided with:
- Arm Cortex-A720AE application cores (8 clusters x 4 cores)
- Arm Cortex-R52 real-time cores (3 clusters x 4 cores)
- Arm Cortex-M33 system control processor
Signed-off-by: Julien Panis <jpanis@baylibre.com>
The multifunctional interface (MFIS) provides an interface
between the different CPU core domains (AP/RT, AP/SCP and
RT/SCP).
Signed-off-by: Julien Panis <jpanis@baylibre.com>
- Adapt to new MCXW7x clock control
- disable HDI pins
- use flw on non secure range
- enable lpuart1 and use it for uart-pipe, bt-c2h-uart and shell-uart
- configure sys clock to 96MHz for core0 and 48MHz for core1
- use PTA18 for LPUART0 RX pin as workaround for board issue
- fix LPTMR clock source to 32K
- place main stack at beginning of the RAM to workaround boot issue
- move shared memory to third bank (instead of the second) - last 8K
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Adding missing comp3 & comp4 node to g4 (all g4 have 4 comparators).
Adding missing comp5, comp6 & comp7 to stm32g473 (all g473 and derived
types have 7 comparators).
Add configdefaults for SHARED_IRQ_MAX_NUM_CLIENTS and SHARED_INTERRUPTS
to the soc's Kconfig.defconfig.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
Alif MRAM is a random access non-volatile memory that is directly
mapped to the address space of the application core and is available
from reset. A flash driver is not yet available for this device. So
remove "soc-nv-flash" compatible and support for the "fixed-partitions"
from the MRAM node. Fix the board dts files as per this change. This
correctly makes the MRAM node simply a "zephyr,memory-region" so that
the linker can place the ROM image there.
Note that this fix has already been made for the Balletto family
SoC/boards.
Related-to: #107737
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add a display driver for monochrome and grayscale LED matrices driven by
charlieplexed GPIOs. With N GPIO lines such a matrix can drive up to
N*(N-1) LEDs: each pixel sits between an ordered pair of lines and is lit
by driving one line high and one low while every other line is held at
high impedance. Only one LED is lit at a time; a timer scans the pixels
fast enough for persistence of vision.
The driver implements the display API. It keeps a per-pixel framebuffer
and uses a counter device as the scan time source, lighting the next
pixel on each top-value callback. Grayscale is produced by duty
modulation over a configurable number of sub-frames. To stay portable
across SoCs it drives the matrix purely through the generic GPIO API,
configuring the inactive lines as disconnected to obtain the required
high-impedance state rather than touching the GPIO registers directly.
The GPIO bank, the per-pixel high/low pin-pair map, the scan timer,
refresh rate and grayscale depth are all described in devicetree through
the new charlieplex-led-matrix binding.
Signed-off-by: Tyler Baker <tyler.baker@oss.qualcomm.com>
Assisted-by: Claude Code:claude-opus-4.8
Use min/max DT properties instead of providing an informative
only range description in usb-audio-hp and usb-audio-hs compatible
devices YAML file.
This change provides a cleaner build time error trace message when
the values are out of bounds while previously implementation relied
on these values being stored in 16-bit fields.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Clarify that the range information for source-pdos, sink-pdos,
sink-vdos and sink-vdos-v1 DT properties in usb-c-connect DT YAML
file relate to the number of elements in the property array, not
the elements value ranges.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Use min/max DT properties for reset num-resets DT properties to factorize
documentation and build time check of the property values against its
valid range.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Use min/max DT properties for ADC nchannels DT properties to factorize
documentation and build time check of the property values against its
valid range.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add the device tree for the ESP32-P4 SoC: HP-core peripherals
(cpu, intc, gpio, uart, i2c, spi, dma, ledc, etc.), LP-core
memory regions, on-chip LDO regulator node and the LP-core
specific dtsi.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- Add EDMA1 controller node at base address 0x44000000.
- 32 DMA channels with 32 interrupt lines.
- EDMA version 4 compatible (compatible = "nxp,mcux-edma").
- Node is left disabled by default; boards opt in.
Signed-off-by: Qiang Zhang <qiang.zhang_6@nxp.com>
SPI_SILABS_SIWX91X_GSPI_DMA and SPI_SILABS_SIWX91X_GSPI_DMA_MAX_BLOCKS are
redundant. We can achieve the same by checking if
SPI_SILABS_SIWX91X_GSPI_DMA_MAX_BLOCKS > 0.
Then, rather than pulling the DMA if one device use it, automatically use
the DMA it exist (the user can still disable it by settings DMA_MAX_BLOCKS
== 0).
Thanks to that change, we can remove allthe #ifdef in the SPI driver.
A test in spi_siwx91x_is_dma_enabled_instance() is sufficient to make the
DMA relative functions orphans.
Then, we can enable the dma instances in the board DTS, so the user just
have to set DMA=y to enable DMA in the drivers.
The two errors cases are:
- DMA=y while referenced DMA instance in the DT is disabled. The user get
a compilation error
- DMA=n (or DMA driver is disabled) but the user explicitly set
DMA_MAX_BLOCKS > 0. The user get an error during runtime.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
SiWx91x provide two DMA hardware block: GPDMA and UDMA, The GPDMA is
properly named: silabs,gpdma. However, the UDMA is named
"silabs,siwx91x-dma" without any reference to the hardware block it is
supposed to run.
Rename the UDMA driver to fix this inconsistency.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add build targets for nRF93M1 DK board which includes
nRF54L15 as a host MCU.
Bulk of the board definitions are copied from nRF54L15DK.
Main differences:
* The console UART is changed to uart20 as uart30 is routed to modem
* Few GPIO hogs to control the modem and UART switches
* nPM1300 PMIC set up to enable various voltages on board
Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
Some configurations of the DesignWare IP support concurrent XIP
(memory mapping) as part of the IP. The driver currently supports
concurrent XIP using a software workaround and this HW feature is not
yet supported by the driver. However, if concurrent XIP is supported as
well as write XIP not being supported, this will introduce a new
register called XIPSER which this commit adds support for.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Some configurations of the designware IP support write access but not
all. Therefore, this is a configurable devicetree option to enable or
disable support for the mem-map (memory mapped) write registers. Otherwise,
devices that don't support this will come into a bus fault.
signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Update devicetree binding examples to allocate all Bosch M_CAN RX FIFO
elements to RX FIFO0.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Uses generic nomenclature for TDK ntcg series NTC thermistors, which use a
naming scheme that indicates their resistance (R25) and beta (B25/85)
values. Compensation tables are identical for parts with the same
resistance and beta values.
Signed-off-by: Dan Mangum <georgedanielmangum@gmail.com>
The M5Stack PaperColor is an ESP32-S3R8 based development board with a
4-inch Spectra 6 e-paper display.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
Implement the M5PM1 watchdog as a Zephyr watchdog controller child
of the MFD device.
The driver supports a single reset-only timeout channel with one-second
granularity (1 to 255 s).
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
Expose the M5PM1 switchable power rails as fixed-voltage regulator devices
child of the MFD device. The driver supports enabling and disabling the 3.3
V DCDC, 3.3 V LDO, and 5 V boost outputs via the PMIC power config
register.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
Expose the M5PM1 GPIO bank as a Zephyr GPIO controller child of the MFD
device. The driver supports five pins with input/output configuration,
pull-up/pull-down, and open-drain outputs; pin interrupts are not
supported.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
Expose the M5PM1 on-chip ADC as a Zephyr ADC controller child of the MFD
device.
The driver supports rail monitoring channels (VREF, VBAT, VIN, 5VOUT),
GPIO1/GPIO2 inputs via the ADC mux, and an internal temperature channel
at 12-bit resolution.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
The M5PM1 is a small companion microcontroller used on M5Stack boards to
provide power management (battery charging, switchable rails), a small
bank of GPIOs, and an on-chip ADC.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-4.7
Adds devicetree bindings for the Infineon HPPASS Analog Subsystem MFD
parent. Also adds bindings for the HPPASS Autonomous Controller state
table entries. Adds dt-bindings header file for HPPASS trigger sources
and AC condition/action codes.
infineon,hppass-analog MFD parent covers subsystem base address,
HPPASS interrupt, startup initialization timing, and trigger I/O
routing.
infineon,hppass-ac-state defines bindings for one STT (state-transition
table) row. Two options are provided, a basic default STT that handles
HPPASS initialization, and an advanced mode that allows a user to supply
a custom STT tailored for the application.
Adds hppass_analog0 to device tree for both psc3.dtsi and psc3_s.dtsi.
Assisted-by: Github Copilot:claude-opus-4.7
Signed-off-by: John Batch <john.batch@infineon.com>
Add the driver itself and Kconfig/CMakeLists/dts/bindings related to it.
Other files and libraries needed are in Silabs' dedicated folder
hal_silabs (modules/hal/silabs).
Co-Authored-by: David Boullie <David.Boullie@silabs.com>
Co-Authored-by: Sree Sreerajatha <sree.sreerajatha@silabs.com>
Signed-off-by: David Boullie <David.Boullie@silabs.com>
is_sg_enabled, sg_velocity_check_interval_ms and
sg_threshold_velocity should not be dts properties as they
are not actuallly hardware configurations.
dropping the check for is_sg_enabled in init routines, since
the configuration happens at runtime now.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
