drivers: clock: Add dumb clock driver for SiWx91x
This driver is mostly the initial seed for further implementation of a real clock driver. It doesn't allow the user to choose the clock source for the various peripherals. The driver hardcodes some sane values. Note that for now, the driver snps,designware-i2c does not support "clocks" attribute. So this patch hardcode the clock configuration in the init of the clock driver. Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
This commit is contained in:
Jérôme Pouiller
Benjamin Cabé
parent
931e7cfeca
commit
ffb1c0de61
6 changed files with 238 additions and 0 deletions
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@ -26,6 +26,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clo
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC clock_control_rv32m1_pcc.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_INFINEON_CAT1 clock_control_ifx_cat1.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAM clock_control_sam_pmc.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SILABS_SIWX91X clock_control_silabs_siwx91x.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SILABS_SERIES clock_control_silabs_series.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_PLL clock_control_si32_pll.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_AHB clock_control_si32_ahb.c)
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@ -102,6 +102,8 @@ source "drivers/clock_control/Kconfig.arm_scmi"
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source "drivers/clock_control/Kconfig.silabs"
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source "drivers/clock_control/Kconfig.siwx91x"
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source "drivers/clock_control/Kconfig.wch_rcc"
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endif # CLOCK_CONTROL
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15
drivers/clock_control/Kconfig.siwx91x
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15
drivers/clock_control/Kconfig.siwx91x
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@ -0,0 +1,15 @@
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# Copyright (c) 2024 Silicon Laboratories Inc.
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# SPDX-License-Identifier: Apache-2.0
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config CLOCK_CONTROL_SILABS_SIWX91X
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bool "SiWx91x clock control driver"
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default y
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depends on DT_HAS_SILABS_SIWX91X_CLOCK_ENABLED
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help
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Enable clock management on Silicon Labs SiWx91x chips. This driver
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includes support for HP (High Performace), ULP (Ultra Low Power), and
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ULP VBAT clocks.
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The original hardware allow to customize the various clocks offered for
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every devices. This driver does not provide such customizations. It
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just hardcodes sane default parameters for every devices.
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186
drivers/clock_control/clock_control_silabs_siwx91x.c
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186
drivers/clock_control/clock_control_silabs_siwx91x.c
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@ -0,0 +1,186 @@
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/* Copyright (c) 2024 Silicon Laboratories Inc.
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* SPDX-License-Identifier: Apache-2.0
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*
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* Poor man driver for 917 clocks. 917 includes High Performace (HP) clock
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* (@46000000), Ultra Lower Power (ULP) clock (@24041400) and ULP VBAT (@24048000)
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*
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*/
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#include <zephyr/dt-bindings/clock/silabs/siwx91x-clock.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/logging/log.h>
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#include "rsi_power_save.h"
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#include "rsi_rom_ulpss_clk.h"
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#include "rsi_rom_clks.h"
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#include "clock_update.h"
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#include "sl_si91x_clock_manager.h"
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#define DT_DRV_COMPAT silabs_siwx91x_clock
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LOG_MODULE_REGISTER(siwx91x_clock, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
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struct siwx91x_clock_data {
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uint32_t enable;
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};
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static int siwx91x_clock_on(const struct device *dev, clock_control_subsys_t sys)
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{
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struct siwx91x_clock_data *data = dev->data;
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uintptr_t clockid = (uintptr_t)sys;
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switch (clockid) {
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case SIWX91X_CLK_ULP_UART:
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RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_UART);
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RSI_ULPSS_UlpUartClkConfig(ULPCLK, ENABLE_STATIC_CLK,
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false, ULP_UART_ULP_MHZ_RC_CLK, 1);
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break;
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case SIWX91X_CLK_ULP_I2C:
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RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_I2C);
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RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_I2C_CLK, ENABLE_STATIC_CLK);
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break;
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case SIWX91X_CLK_ULP_DMA:
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RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_UDMA);
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RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_UDMA_CLK, ENABLE_STATIC_CLK);
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break;
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case SIWX91X_CLK_UART1:
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RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI);
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/* RSI_CLK_UsartClkConfig() calls RSI_CLK_PeripheralClkEnable(); */
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RSI_CLK_UsartClkConfig(M4CLK, ENABLE_STATIC_CLK, 0, USART1, 0, 1);
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break;
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case SIWX91X_CLK_UART2:
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RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI);
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/* RSI_CLK_UsartClkConfig() calls RSI_CLK_PeripheralClkEnable(); */
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RSI_CLK_UsartClkConfig(M4CLK, ENABLE_STATIC_CLK, 0, USART2, 0, 1);
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break;
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case SIWX91X_CLK_I2C0:
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RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI);
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RSI_CLK_I2CClkConfig(M4CLK, true, 0);
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break;
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case SIWX91X_CLK_I2C1:
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RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI);
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RSI_CLK_I2CClkConfig(M4CLK, true, 1);
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break;
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case SIWX91X_CLK_DMA0:
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RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI);
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RSI_CLK_PeripheralClkEnable(M4CLK, UDMA_CLK, ENABLE_STATIC_CLK);
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break;
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default:
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return -EINVAL;
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}
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data->enable |= BIT(clockid);
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return 0;
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}
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static int siwx91x_clock_off(const struct device *dev, clock_control_subsys_t sys)
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{
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struct siwx91x_clock_data *data = dev->data;
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uintptr_t clockid = (uintptr_t)sys;
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switch (clockid) {
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case SIWX91X_CLK_ULP_I2C:
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RSI_ULPSS_PeripheralDisable(ULPCLK, ULP_I2C_CLK);
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break;
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case SIWX91X_CLK_ULP_DMA:
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RSI_ULPSS_PeripheralDisable(ULPCLK, ULP_UDMA_CLK);
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break;
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case SIWX91X_CLK_UART1:
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RSI_CLK_PeripheralClkDisable(M4CLK, USART1_CLK);
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break;
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case SIWX91X_CLK_UART2:
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RSI_CLK_PeripheralClkDisable(M4CLK, USART2_CLK);
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break;
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case SIWX91X_CLK_DMA0:
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RSI_CLK_PeripheralClkDisable(M4CLK, UDMA_CLK);
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break;
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case SIWX91X_CLK_ULP_UART:
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case SIWX91X_CLK_I2C0:
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case SIWX91X_CLK_I2C1:
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/* Not supported */
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return 0;
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default:
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return -EINVAL;
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}
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data->enable &= ~BIT(clockid);
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return 0;
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}
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static int siwx91x_clock_get_rate(const struct device *dev, clock_control_subsys_t sys,
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uint32_t *rate)
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{
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uintptr_t clockid = (uintptr_t)sys;
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switch (clockid) {
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case SIWX91X_CLK_ULP_UART:
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*rate = RSI_CLK_GetBaseClock(ULPSS_UART);
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return 0;
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case SIWX91X_CLK_UART1:
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*rate = RSI_CLK_GetBaseClock(M4_USART0);
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return 0;
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case SIWX91X_CLK_UART2:
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*rate = RSI_CLK_GetBaseClock(M4_UART1);
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return 0;
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default:
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/* For now, no other driver need clock rate */
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return -EINVAL;
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}
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}
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static enum clock_control_status siwx91x_clock_get_status(const struct device *dev,
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clock_control_subsys_t sys)
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{
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struct siwx91x_clock_data *data = dev->data;
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uintptr_t clockid = (uintptr_t)sys;
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if (data->enable & BIT(clockid)) {
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return CLOCK_CONTROL_STATUS_ON;
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} else {
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return CLOCK_CONTROL_STATUS_OFF;
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}
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}
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static int siwx91x_clock_init(const struct device *dev)
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{
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SystemCoreClockUpdate();
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/* Use SoC PLL at configured frequency as core clock */
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sl_si91x_clock_manager_m4_set_core_clk(M4_SOCPLLCLK, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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/* Use interface PLL at configured frequency as peripheral clock */
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sl_si91x_clock_manager_set_pll_freq(INFT_PLL, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
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PLL_REF_CLK_VAL_XTAL);
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/* FIXME: Currently the clock consumer use clocks without power on them.
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* This should be fixed in drivers. Meanwhile, get the list of required
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* clocks using DT labels.
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*/
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ulpi2c), okay)
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siwx91x_clock_on(dev, (clock_control_subsys_t)SIWX91X_CLK_ULP_I2C);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c0), okay)
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siwx91x_clock_on(dev, (clock_control_subsys_t)SIWX91X_CLK_I2C0);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay)
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siwx91x_clock_on(dev, (clock_control_subsys_t)SIWX91X_CLK_I2C1);
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#endif
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return 0;
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}
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static DEVICE_API(clock_control, siwx91x_clock_api) = {
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.on = siwx91x_clock_on,
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.off = siwx91x_clock_off,
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.get_rate = siwx91x_clock_get_rate,
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.get_status = siwx91x_clock_get_status,
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};
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#define SIWX91X_CLOCK_INIT(p) \
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static struct siwx91x_clock_data siwx91x_clock_data_##p; \
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DEVICE_DT_INST_DEFINE(p, siwx91x_clock_init, NULL, &siwx91x_clock_data_##p, NULL, \
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PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \
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&siwx91x_clock_api);
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DT_INST_FOREACH_STATUS_OKAY(SIWX91X_CLOCK_INIT)
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18
dts/bindings/clock/silabs,siwx91x-clock.yaml
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18
dts/bindings/clock/silabs,siwx91x-clock.yaml
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@ -0,0 +1,18 @@
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# Copyright (c) 2024 Silicon Laboratories Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: Clocks embedded on Silabs SiWx91x chips
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compatible: "silabs,siwx91x-clock"
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include: [clock-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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"#clock-cells":
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const: 1
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clock-cells:
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- clkid
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16
include/zephyr/dt-bindings/clock/silabs/siwx91x-clock.h
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16
include/zephyr/dt-bindings/clock/silabs/siwx91x-clock.h
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@ -0,0 +1,16 @@
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/* Copyright (c) 2024 Silicon Laboratories Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_SIWX91X_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_SIWX91X_CLOCK_H_
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#define SIWX91X_CLK_ULP_UART 0
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#define SIWX91X_CLK_ULP_I2C 1
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#define SIWX91X_CLK_ULP_DMA 2
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#define SIWX91X_CLK_UART1 3
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#define SIWX91X_CLK_UART2 4
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#define SIWX91X_CLK_I2C0 5
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#define SIWX91X_CLK_I2C1 6
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#define SIWX91X_CLK_DMA0 7
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#endif
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