Add pin control definitions for SPI master signals (CLK, MISO, MOSI,
and SELECT lines) for SCB0 and SCB1 on the PSoC4100TP 64-TQFP package.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
fixes a bunch of errors (eg ADL1234 instead of AD1234) and inconsistencies
in the naming of the Analog Devices ADC bindings.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
- exit-latency-us is SOC wake time. Updated based on measurements
- exit-latency-us increased for PM3 on frdm_rw612 to match
measurements on that board.
- min-residency-us depends on use-case, moved to the board DTS, based
on measurements
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Removes resource reservation for cpuflpr from the cpuapp build and
only applies it when either of the flpr snippets are used
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This change renames the Infineon BT-HCI UART driver source
and binding file to allow reuse across all Infineon AIROC
connectivity chips that use HCI UART transport.
No functional changes
Signed-off-by: Merin George <merin.george@infineon.com>
Add the `ranges` property to the flash node on RP2040-based boards to
correctly specify the base address and size for child nodes. This aligns
the board device trees with expected Zephyr DT conventions and ensures
proper address translation for flash partitions and other child nodes.
Signed-off-by: David Schneider <schneidav81@gmail.com>
- Adds the common dtsi files based on memory configuration and pin
configuration
- Adds the gpio nodes in pic32cm_pl10 series
- Adds the list of supported socs
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
- Add `max-bitrate-supported` property to indicate the maximum
bitrate that the channel can support.
- Update `max-bitrate-supported` property value for all Renesas RA
devices
- Update driver i2c_renesas_ra_iic.c to check `clock-frequency`
property and bitrate runtime configure is correct
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
The GINT peripheral provides grouped GPIO interrupt
functionality, allowing multiple pins to be combined
into a single interrupt source.
Support the peripheral in interrupt controller
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
add initial version of devicetree for amebaG2 SOC.
amebaG2 devicetree file is main platform dtsi file, which should
be included from board dts (e.g rtl8721f_evb.dts)
Signed-off-by: zjian zhang <zjian_zhang@realsil.com.cn>
Add missing clock property to spi00 nodes. Add missing clock property to
uart00 node in nrf7120.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Since, commit 2f7d13840f ("kconfig: Fix CONFIG_FLASH_LOAD_OFFSET for non-0
starting addresses"), the way to compute offsets in the flash memory has
changed.
With this change, the arguments passed to siwx91x_isp_prepare.py were not
correct anymore and "west flash" ended up with:
ERROR: Waiting for flashloader failed: 108 - Checksum error
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add property for overriding the maximum number of hardware message buffers
used for RX filters on a per-instance basis.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The maximum number of RX filters is limited by the number of message
buffers, which cannot exceed 128. Add a range to the Kconfig option
imposing this.
Remove artificial build-time check on CONFIG_CAN_MCUX_FLEXCAN_MAX_FILTERS
being larger than zero, as transmit-only configuration is otherwise fully
supported.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The flash0 physical address in the node name did not
match the starting address in the reg property. This
part implements 352KB code SRAM starting at 0xC0000.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Fix mismatch between unit address of the power domain nodes and the value
passed via the "reg" property.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Add device tree node for the Broadcom iProc RNG200 hardware
random number generator found on BCM2711 SoC
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Now that STM32WBA6 also uses the st,stm32n6-otghs compatible, reword the
description to better fit its use.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Update hal_stm32 revision so that SPI pinctrl are configured with a
very-high-speed slew rate by default.
Rename debug_jtrst_pb4 to debug_njtrst_pb4 for U5 and WBA. For WBA65,
remove the now useless swj_port redefinition.
For WBA65, remove the USB OTG pinctrl. As per RefMan RM0515, "PD6 and PD7
provide USB OTG_HS functions, but they cannot be used for any other
function, including GPIO. When USB OTG_HS is not used, PD6 and PD7 must be
kept in analog mode."
Change the compatible to the N6 one which do not require pinctrl.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add devicetree binding for the SiFli SF32LB series eFuse OTP memory
controller. The eFuse provides 128 bytes (4 banks x 32 bytes) of
one-time programmable storage.
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
Correct GIC addresses to match ARM Cortex-R8 TRM PERIPHBASE specification.
GIC must be at fixed offsets from PERIPHBASE (0xAE000000)
- Distributor: 0xAE001000 (PERIPHBASE + 0x1000)
- CPU Interface: 0xAE000100 (PERIPHBASE + 0x100)
Updated device tree, MPU regions, and Renode configuration to use
correct addresses and add required memory protection.
Signed-off-by: Raja Shahzaib <rshahzaib077@gmail.com>
