replace BUILD_ASSERT for fifo-watermark with min/max in bindings
replace all enums with min/max with their corresponding ranges
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
use min/max for fifo-watermark in bosch,bmi08x-gyro.yaml
and bosch,bmi08x-accel.yaml
drop BUILD_ASSERT in bmi08x_gyro.c
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
use min/max for proximity-pulse-count, proximity-high-threshold
proximity-low-threshold, proximity-led-drive-strength,
proximity-interrupt-filter and wait-time-factor
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
Add nordic-tz-secure and nordic-tz-nonsecure nodes describing the
TrustZone-M partition layout. They reference the existing partition
leaves by phandle; the leaves are unchanged.
Signed-off-by: Dag Erik Gjørvad <dag.erik.gjorvad@nordicsemi.no>
Add nordic-tz-secure and nordic-tz-nonsecure nodes describing the
NS-build flash footprint. They reference the existing partition
leaves by phandle; the leaves are unchanged.
Signed-off-by: Dag Erik Gjørvad <dag.erik.gjorvad@nordicsemi.no>
Add nordic-tz-secure and nordic-tz-nonsecure nodes describing the
NS-build flash footprint. They reference the existing partition
leaves by phandle; the leaves are unchanged.
Signed-off-by: Dag Erik Gjørvad <dag.erik.gjorvad@nordicsemi.no>
Add nordic-tz-secure and nordic-tz-nonsecure nodes describing the
NS-build flash footprint. They reference the existing partition
leaves by phandle; the leaves are unchanged.
Signed-off-by: Dag Erik Gjørvad <dag.erik.gjorvad@nordicsemi.no>
Add nordic-tz-secure and nordic-tz-nonsecure nodes describing the
NS-build flash footprint. They reference the existing partition
leaves by phandle; the leaves are unchanged.
Signed-off-by: Dag Erik Gjørvad <dag.erik.gjorvad@nordicsemi.no>
Add nordic-tz-secure and nordic-tz-nonsecure nodes describing the
NS-build flash footprint. They reference the existing partition
leaves by phandle; the leaves are unchanged.
Signed-off-by: Dag Erik Gjørvad <dag.erik.gjorvad@nordicsemi.no>
Add nordic,tz-secure and nordic,tz-nonsecure. Each describes a
security state's flash footprint via code-partitions and
data-partitions phandle lists pointing at zephyr,mapped-partition
leaves.
Signed-off-by: Dag Erik Gjørvad <dag.erik.gjorvad@nordicsemi.no>
The qspi flash controller uses the Serial Memory Interface (SMIF) to
interact with an external memory. This is done through dedicated
data pins which reside in the SMIF HW block. These were not exposed
up until now in the Infineon devices because the extended boot takes
care of initializing the pins properly when booting from external flash.
However this might not always be the case so expose the pin info and
configuration. Additionally, correct the flash controller address to
match the SMIF CORE base address corresponding to the SMIF instance
in use.
Assisted-by: Claude:claude-opus-4.7
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Document SF32LB52x slew-rate pinctrl support. The public property
uses 0 for slow slew rate and 1 for fast slew rate, with slow as the
default.
Also document that PA39-PA42 do not support slew-rate because bit 8
is MODE on those pads.
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
Nuvoton USBD/HSUSBD peripherals support VBUS detect functionality, but
some PCB designs may choose to use mutually exclusive USB-C peripheral
for VBUS detection. In this case, the USB controller backed VBUS detect
functionality won't work and needs to be disabled.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
- Read write_block_size from devicetree (default 4 in binding) to
allow board-level override for finer write granularity.
- Add CONFIG_FLASH_MCUX_XSPI_WRITE_BUFFER (default n) to copy
write data to a RAM buffer before transfer, preventing faults
when source data resides in flash and padding transfer size to
4-byte boundary for the XSPI IP Tx limitation.
- When write buffer is disabled, reject non-4-byte-aligned offset
or length with -EINVAL.
Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
To communicate with the modem core the application core needs to have
three separate partitions defined:
- cpuapp_cpucell_ipc_shm_ctrl: for controll messages.
- cpuapp_cpucell_ipc_shm_heap: for data from app core to cell core.
- cpucell_cpuapp_ipc_shm_heap: for data from cell core to app core.
Signed-off-by: Lucas van der Ploeg <lucas.vanderploeg@nordicsemi.no>
Add the Devicetree include file for Allwinner sun50i-h618 SoC,
defining CPU cores, timer, interrupt controller, and UART0.
Signed-off-by: Khai Do <dovankhai97@gmail.com>
Honor regulator-init-microvolt and the boot-on / always-on
properties at init so on-chip LDOs come up before the kernel
runs.
Switch the binding from the custom espressif,ldo-channel
property to a standard reg + unit-address layout, and read the
channel via DT_REG_ADDR().
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Updated bbram compatible in mec5 dtsi
Added macro required to port the bbram driver for MEC174x/5x.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Change interrupt controller bindings to use consistent cell name for IRQ
type field. This change was motivated by the fact that some controllers
used cell name "sense" while others used "flags".
Therefore, standardize all interrupt controller bindings to use "flags"
as the cell name, aligning with the IRQ_CONNECT() macro parameter name
in include/zephyr/irq.h.
Updated interrupt controller bindings:
- intel,ioapic
- intel,loapic
- cdns,xtensa-core-intc
- intel,ace-intc
- intel,cavs-intc
- snps,designware-intc
- mediatek,adsp_intc
This is a treewide breaking change that affects interrupt controller
bindings throughout the codebase.
Suggested-by: Jan Kiszka <jan.kiszka@siemens.com>
Suggested-by: Andrew Davis <afd@ti.com>
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Add I2C0, I2C1, I2C3, I2C4, I2C5 and I2C6 devicetree nodes
for Broadcom BCM2711 SoC.
Add I2C0 and I2C1 pinctrl groups to bcm283x-pinctrl.dtsi
and I2C3, I2C4, I2C5 and I2C6 pinctrl groups to bcm2711-pinctrl.dtsi
to expose alternative GPIO mappings supported by the hardware.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add driver for NXP MCUX Segment LCD (SLCD) controller to support
segment-style auxiliary displays.
The driver provides a unified implementation that handles both
the SLCD controller (nxp,slcd) and a generic SLCD panel.
It supports the generic SLCD panel with common header and binding
which includes the following panel features:
- Segment types(7, 14, 16 segments)
- Configurable front plane pins and back plane COMs
- pin/COM for each segment
- Optional pin/COM for each indicator
- Optional colon/dot indicators
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Currently ZynqMP board setups do not appear to be using the flash0 node
which is used for running in XIP mode from QSPI flash storage. Mark this
node as disabled to avoid tripping up the
drivers.flash.common.disable_spi_nor tests, which would otherwise try to
build with FLASH enabled and SPI_NOR disabled.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add a driver for the Generic Quad SPI hardware that is part of the
Xilinx MPSoC. This is mostly commonly used with QSPI flash devices which
are also used for initial image loading, but can also be used with other
SPI devices.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Replace fixed-partitions with ranges and add
compatible = "zephyr,mapped-partition" to all partitions in
rtl87x2g.dtsi, rtl8752h.dtsi, and all rtl87x2g_evb_a/rtl8752h_evb
board DTS files.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Add TDM DMA driver for AMD Audio Co-Processor 7.0. This includes:
- DMA driver (dma_acp_tdm.c) with support for memory-to-device and
device-to-memory transfers using ACP DMA engine
- Device tree bindings and node for ACP TDM DMA controller
- Kconfig and CMake build integration
Signed-off-by: Siva Subramanian Ravi Saravanan <sravisar@amd.com>
Co-authored-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
Add TDM DAI driver and ACP 7.0 register
definitions for AMD Audio Co-Processor. This includes:
- TDM DAI driver (tdm_dai.c) with support for I2S format
- ACP 7.0 chip register definitions and offset mappings
- Device tree bindings and nodes for TDM DAI instances
- Kconfig and CMake build integration
Signed-off-by: Siva Subramanian Ravi Saravanan <sravisar@amd.com>
Co-authored-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
Add the possibility to configure the interrupt gpio in one of the
two possiblities:
- GPIO_INT_EDGE_TO_ACTIVE
- GPIO_INT_LEVEL_ACTIVE
Default is GPIO_INT_EDGE_TO_ACTIVE, which matches with old fixed
configuration.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Add support for using RTI hardware as system timer:
- Add headers, driver code, Kconfig, and bindings for TI RTI Timer
- Make changes in CMakeLists.txt and Kconfig to support ti_rti_timer
- Add documentation and usage instructions in bindings file.
NOTE: Each RTI has 2 Counter blocks, 4 Counter Compare blocks.
This driver assumes that Counter block 0, Compare block 0 of
chosen RTI instance are used as RTI Timer.
Signed-off-by: Shreyas Shankar <s-shankar@ti.com>
Fix devicetree coding style regarding whitespaces through the tree.
This affects code snippets inside documentation, comments, error messages
as to encourage a style that passes CI. Follow-up of #101619
Signed-off-by: Josuah Demangeon <me@josuah.net>
Keep the RNG node disabled at the SoC level so board-specific
DTS files remain responsible for enabling the hardware when
appropriate.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Introduce new properties for ST HCI SPI to handle the new changes
required by x-nucleo-wba25a1 efficiently.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Added support for autanalog PRB for PSE84.
This implementation uses the shared autonomous controller (AC) MFD
with the other autanalog drivers.
The PRB is a programmable reference block inside the autonomous
(aut) analog subsystem. It is controlled using the autonomous
controller (AC), which is a programmable state machine. The AC is
shared across all autonomous analog peripherals including the
SAR, PRB, PTComp, CTB, and CTDAC.
The PRB contains two variable voltage references derived from
either VDDA(1.8V) or VGBR(0.9V). These need to be configured
together and accessed using the AC. A PRB MFD is used to bring
together the two voltage reference configurations. AC MFD then
references the combined PRB MFD configuration, and brings together
all other autanalog peripherals into a single AC setup for the
application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
