drivers: eth: add driver for ENC424J600 Ethernet Controller

Add driver for ENC424J600 Ethernet Controller.

Signed-off-by: Johann Fischer <j.fischer@phytec.de>
This commit is contained in:
Johann Fischer 2019-08-16 00:57:20 +02:00 committed by Jukka Rissanen
commit d8d7782790
6 changed files with 1129 additions and 0 deletions

View file

@ -10,6 +10,7 @@ zephyr_sources_ifdef(CONFIG_ETH_SAM_GMAC
zephyr_sources_ifdef(CONFIG_ETH_STELLARIS eth_stellaris.c)
zephyr_sources_ifdef(CONFIG_ETH_E1000 eth_e1000.c)
zephyr_sources_ifdef(CONFIG_ETH_ENC28J60 eth_enc28j60.c)
zephyr_sources_ifdef(CONFIG_ETH_ENC424J600 eth_enc424j600.c)
zephyr_sources_ifdef(CONFIG_ETH_MCUX eth_mcux.c)
zephyr_sources_ifdef(CONFIG_ETH_SMSC911X eth_smsc911x.c)
zephyr_sources_ifdef(CONFIG_ETH_STM32_HAL eth_stm32_hal.c)

View file

@ -25,6 +25,7 @@ config ETH_INIT_PRIORITY
so that it can start before the networking sub-system.
source "drivers/ethernet/Kconfig.enc28j60"
source "drivers/ethernet/Kconfig.enc424j600"
source "drivers/ethernet/Kconfig.mcux"
source "drivers/ethernet/Kconfig.e1000"
source "drivers/ethernet/Kconfig.sam_gmac"

View file

@ -0,0 +1,46 @@
# Kconfig - ENC424J600 Ethernet driver configuration options
#
# Copyright (c) 2019 PHYTEC Messtechnik GmbH
#
# SPDX-License-Identifier: Apache-2.0
#
menuconfig ETH_ENC424J600
bool "ENC424J600C Ethernet Controller"
depends on SPI
help
ENC424J600C Stand-Alone Ethernet Controller
with SPI Interface
if ETH_ENC424J600
config ETH_ENC424J600_RX_THREAD_STACK_SIZE
int "Stack size for internal incoming packet handler"
default 800
help
Size of the stack used for internal thread which is ran for
incoming packet processing.
config ETH_ENC424J600_RX_THREAD_PRIO
int "Priority for internal incoming packet handler"
default 2
help
Priority level for internal thread which is ran for incoming
packet processing.
config ETH_ENC424J600_TIMEOUT
int "IP buffer timeout"
default 100
help
Given timeout in milliseconds. Maximum amount of time
that the driver will wait from the IP stack to get
a memory buffer before the Ethernet frame is dropped.
config ETH_ENC424J600_0_GPIO_SPI_CS
bool "Manage SPI CS through a GPIO pin"
help
This option is useful if one needs to manage SPI CS through a GPIO
pin to by-pass the SPI controller's CS logic.
endif

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@ -0,0 +1,758 @@
/* ENC424J600 Stand-alone Ethernet Controller with SPI
*
* Copyright (c) 2016 Intel Corporation
* Copyright (c) 2019 PHYTEC Messtechnik GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr.h>
#include <device.h>
#include <string.h>
#include <errno.h>
#include <drivers/gpio.h>
#include <drivers/spi.h>
#include <net/net_pkt.h>
#include <net/net_if.h>
#include <net/ethernet.h>
#include <ethernet/eth_stats.h>
#include "eth_enc424j600_priv.h"
LOG_MODULE_REGISTER(ethdrv, CONFIG_ETHERNET_LOG_LEVEL);
static void enc424j600_write_sbc(struct device *dev, u8_t cmd)
{
struct enc424j600_runtime *context = dev->driver_data;
u8_t buf[2] = { cmd, 0xFF };
const struct spi_buf tx_buf = {
.buf = buf,
.len = 1,
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1
};
spi_write(context->spi, &context->spi_cfg, &tx);
}
static void enc424j600_write_sfru(struct device *dev, u8_t addr,
u16_t value)
{
struct enc424j600_runtime *context = dev->driver_data;
u8_t buf[4];
const struct spi_buf tx_buf = {
.buf = buf,
.len = sizeof(buf)
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1
};
buf[0] = ENC424J600_NBC_WCRU;
buf[1] = addr;
buf[2] = value;
buf[3] = value >> 8;
spi_write(context->spi, &context->spi_cfg, &tx);
}
static void enc424j600_read_sfru(struct device *dev, u8_t addr,
u16_t *value)
{
struct enc424j600_runtime *context = dev->driver_data;
u8_t buf[4];
const struct spi_buf tx_buf = {
.buf = buf,
.len = 2
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1
};
struct spi_buf rx_buf = {
.buf = buf,
.len = sizeof(buf),
};
const struct spi_buf_set rx = {
.buffers = &rx_buf,
.count = 1
};
buf[0] = ENC424J600_NBC_RCRU;
buf[1] = addr;
if (!spi_transceive(context->spi, &context->spi_cfg, &tx, &rx)) {
*value = ((u16_t)buf[3] << 8 | buf[2]);
} else {
LOG_DBG("Failure while reading register 0x%02x", addr);
*value = 0U;
}
}
static void enc424j600_modify_sfru(struct device *dev, u8_t opcode,
u16_t addr, u16_t value)
{
struct enc424j600_runtime *context = dev->driver_data;
u8_t buf[4];
const struct spi_buf tx_buf = {
.buf = buf,
.len = sizeof(buf)
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1
};
buf[0] = opcode;
buf[1] = addr;
buf[2] = value;
buf[3] = value >> 8;
spi_write(context->spi, &context->spi_cfg, &tx);
}
#define enc424j600_set_sfru(dev, addr, value) \
enc424j600_modify_sfru(dev, ENC424J600_NBC_BFSU, addr, value)
#define enc424j600_clear_sfru(dev, addr, value) \
enc424j600_modify_sfru(dev, ENC424J600_NBC_BFCU, addr, value)
static void enc424j600_write_phy(struct device *dev, u16_t addr, u16_t data)
{
u16_t mistat;
enc424j600_write_sfru(dev, ENC424J600_SFR2_MIREGADRL, addr);
enc424j600_write_sfru(dev, ENC424J600_SFR3_MIWRL, data);
do {
k_busy_wait(ENC424J600_PHY_ACCESS_DELAY);
enc424j600_read_sfru(dev, ENC424J600_SFR3_MISTATL, &mistat);
} while ((mistat & ENC424J600_MISTAT_BUSY));
}
static void enc424j600_read_phy(struct device *dev, u16_t addr, u16_t *data)
{
u16_t mistat;
enc424j600_write_sfru(dev, ENC424J600_SFR2_MIREGADRL, addr);
enc424j600_write_sfru(dev, ENC424J600_SFR2_MICMDL,
ENC424J600_MICMD_MIIRD);
do {
k_busy_wait(ENC424J600_PHY_ACCESS_DELAY);
enc424j600_read_sfru(dev, ENC424J600_SFR3_MISTATL, &mistat);
} while ((mistat & ENC424J600_MISTAT_BUSY));
enc424j600_write_sfru(dev, ENC424J600_SFR2_MICMDL, 0);
enc424j600_read_sfru(dev, ENC424J600_SFR3_MIRDL, data);
}
static void enc424j600_write_mem(struct device *dev, u8_t opcode,
u8_t *data_buffer, u16_t buf_len)
{
struct enc424j600_runtime *context = dev->driver_data;
u8_t buf[1] = { opcode };
const struct spi_buf tx_buf[2] = {
{
.buf = buf,
.len = 1
},
{
.buf = data_buffer,
.len = buf_len
},
};
const struct spi_buf_set tx = {
.buffers = tx_buf,
.count = 2
};
if (spi_write(context->spi, &context->spi_cfg, &tx)) {
LOG_ERR("Failed to write SRAM buffer");
return;
}
}
static void enc424j600_read_mem(struct device *dev, u8_t opcode,
u8_t *data_buffer, u16_t buf_len)
{
struct enc424j600_runtime *context = dev->driver_data;
u8_t buf[1] = { opcode };
const struct spi_buf tx_buf = {
.buf = buf,
.len = 1
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1
};
struct spi_buf rx_buf[2] = {
{
.buf = NULL,
.len = 1
},
{
.buf = data_buffer,
.len = buf_len
},
};
const struct spi_buf_set rx = {
.buffers = rx_buf,
.count = 2
};
if (spi_transceive(context->spi, &context->spi_cfg, &tx, &rx)) {
LOG_ERR("Failed to read SRAM buffer");
return;
}
}
static void enc424j600_gpio_callback(struct device *dev,
struct gpio_callback *cb,
u32_t pins)
{
struct enc424j600_runtime *context =
CONTAINER_OF(cb, struct enc424j600_runtime, gpio_cb);
k_sem_give(&context->int_sem);
}
static void enc424j600_init_filters(struct device *dev)
{
u16_t tmp;
enc424j600_write_sfru(dev, ENC424J600_SFR1_ERXFCONL,
ENC424J600_ERXFCON_CRCEN |
ENC424J600_ERXFCON_RUNTEN |
ENC424J600_ERXFCON_UCEN |
ENC424J600_ERXFCON_MCEN |
ENC424J600_ERXFCON_BCEN);
if (CONFIG_ETHERNET_LOG_LEVEL == LOG_LEVEL_DBG) {
enc424j600_read_sfru(dev, ENC424J600_SFR1_ERXFCONL, &tmp);
LOG_DBG("ERXFCON: 0x%04x", tmp);
}
}
static void enc424j600_init_phy(struct device *dev)
{
u16_t tmp;
enc424j600_write_phy(dev, ENC424J600_PSFR_PHANA,
ENC424J600_PHANA_ADPAUS_SYMMETRIC_ONLY |
ENC424J600_PHANA_AD100FD |
ENC424J600_PHANA_AD100 |
ENC424J600_PHANA_AD10FD |
ENC424J600_PHANA_AD10 |
ENC424J600_PHANA_ADIEEE_DEFAULT);
if (CONFIG_ETHERNET_LOG_LEVEL == LOG_LEVEL_DBG) {
enc424j600_read_phy(dev, ENC424J600_PSFR_PHANA, &tmp);
LOG_DBG("PHANA: 0x%04x", tmp);
}
enc424j600_read_phy(dev, ENC424J600_PSFR_PHCON1, &tmp);
tmp |= ENC424J600_PHCON1_RENEG;
LOG_DBG("PHCON1: 0x%04x", tmp);
enc424j600_write_phy(dev, ENC424J600_PSFR_PHCON1, tmp);
}
static void enc424j600_setup_mac(struct device *dev)
{
u16_t tmp;
u16_t macon2;
if (CONFIG_ETHERNET_LOG_LEVEL == LOG_LEVEL_DBG) {
enc424j600_read_phy(dev, ENC424J600_PSFR_PHANLPA, &tmp);
LOG_DBG("PHANLPA: 0x%04x", tmp);
}
enc424j600_read_phy(dev, ENC424J600_PSFR_PHSTAT3, &tmp);
if (tmp & ENC424J600_PHSTAT3_SPDDPX_100) {
LOG_INF("100Mbps");
} else if (tmp & ENC424J600_PHSTAT3_SPDDPX_10) {
LOG_INF("10Mbps");
} else {
LOG_ERR("Unknown speed configuration");
}
if (tmp & ENC424J600_PHSTAT3_SPDDPX_FD) {
LOG_INF("full duplex");
enc424j600_read_sfru(dev, ENC424J600_SFR2_MACON2L, &macon2);
macon2 |= ENC424J600_MACON2_FULDPX;
enc424j600_write_sfru(dev, ENC424J600_SFR2_MACON2L, macon2);
enc424j600_write_sfru(dev, ENC424J600_SFR2_MABBIPGL,
ENC424J600_MABBIPG_DEFAULT);
} else {
LOG_INF("half duplex");
}
if (CONFIG_ETHERNET_LOG_LEVEL == LOG_LEVEL_DBG) {
enc424j600_read_sfru(dev, ENC424J600_SFR2_MACON2L, &tmp);
LOG_DBG("MACON2: 0x%04x", tmp);
enc424j600_read_sfru(dev, ENC424J600_SFR2_MAMXFLL, &tmp);
LOG_DBG("MAMXFL (maximum frame length): %u", tmp);
}
}
static int enc424j600_tx(struct device *dev, struct net_pkt *pkt)
{
struct enc424j600_runtime *context = dev->driver_data;
u16_t len = net_pkt_get_len(pkt);
struct net_buf *frag;
u16_t tmp;
LOG_DBG("pkt %p (len %u)", pkt, len);
k_sem_take(&context->tx_rx_sem, K_FOREVER);
enc424j600_write_sfru(dev, ENC424J600_SFR4_EGPWRPTL,
ENC424J600_TXSTART);
for (frag = pkt->frags; frag; frag = frag->frags) {
enc424j600_write_mem(dev, ENC424J600_NBC_WGPDATA, frag->data,
frag->len);
}
enc424j600_write_sfru(dev, ENC424J600_SFR0_ETXSTL,
ENC424J600_TXSTART);
enc424j600_write_sfru(dev, ENC424J600_SFR0_ETXLENL, len);
enc424j600_write_sbc(dev, ENC424J600_1BC_SETTXRTS);
do {
k_sleep(1);
enc424j600_read_sfru(dev, ENC424J600_SFRX_ECON1L, &tmp);
} while (tmp & ENC424J600_ECON1_TXRTS);
if (CONFIG_ETHERNET_LOG_LEVEL == LOG_LEVEL_DBG) {
enc424j600_read_sfru(dev, ENC424J600_SFR0_ETXSTATL, &tmp);
LOG_DBG("ETXSTAT: 0x%04x", tmp);
}
k_sem_give(&context->tx_rx_sem);
return 0;
}
static int enc424j600_rx(struct device *dev)
{
struct enc424j600_runtime *context = dev->driver_data;
const struct enc424j600_config *config = dev->config->config_info;
u8_t info[ENC424J600_RSV_SIZE + ENC424J600_PTR_NXP_PKT_SIZE];
struct net_buf *pkt_buf = NULL;
struct net_pkt *pkt;
u16_t frm_len = 0U;
u32_t status;
u16_t tmp;
k_sem_take(&context->tx_rx_sem, K_FOREVER);
enc424j600_write_sfru(dev, ENC424J600_SFR4_ERXRDPTL,
context->next_pkt_ptr);
if (CONFIG_ETHERNET_LOG_LEVEL == LOG_LEVEL_DBG) {
enc424j600_read_sfru(dev, ENC424J600_SFR4_ERXRDPTL, &tmp);
LOG_DBG("set ERXRDPT to 0x%04x", tmp);
}
enc424j600_read_mem(dev, ENC424J600_NBC_RRXDATA, info,
sizeof(info));
if (CONFIG_ETHERNET_LOG_LEVEL == LOG_LEVEL_DBG) {
enc424j600_read_sfru(dev, ENC424J600_SFR4_ERXRDPTL, &tmp);
LOG_DBG("ERXRDPT is 0x%04x now", tmp);
}
context->next_pkt_ptr = sys_get_le16(&info[0]);
frm_len = sys_get_le16(&info[2]);
status = sys_get_le32(&info[4]);
LOG_DBG("npp 0x%04x, length %u, status 0x%08x",
context->next_pkt_ptr, frm_len, status);
/* frame length without FCS */
frm_len -= 4;
/* Get the frame from the buffer */
pkt = net_pkt_rx_alloc_with_buffer(context->iface, frm_len,
AF_UNSPEC, 0,
config->timeout);
if (!pkt) {
LOG_ERR("Could not allocate rx buffer");
eth_stats_update_errors_rx(context->iface);
goto done;
}
pkt_buf = pkt->buffer;
do {
size_t frag_len;
u8_t *data_ptr;
size_t spi_frame_len;
data_ptr = pkt_buf->data;
/* Review the space available for the new frag */
frag_len = net_buf_tailroom(pkt_buf);
if (frm_len > frag_len) {
spi_frame_len = frag_len;
} else {
spi_frame_len = frm_len;
}
enc424j600_read_mem(dev, ENC424J600_NBC_RRXDATA, data_ptr,
spi_frame_len);
net_buf_add(pkt_buf, spi_frame_len);
/* One fragment has been written via SPI */
frm_len -= spi_frame_len;
pkt_buf = pkt_buf->frags;
} while (frm_len > 0);
if (net_recv_data(context->iface, pkt) < 0) {
net_pkt_unref(pkt);
}
done:
if (context->next_pkt_ptr == ENC424J600_RXSTART) {
tmp = ENC424J600_RXEND - 1;
LOG_DBG("wrap back");
} else {
tmp = context->next_pkt_ptr - 2;
}
enc424j600_write_sfru(dev, ENC424J600_SFR0_ERXTAILL, tmp);
enc424j600_write_sbc(dev, ENC424J600_1BC_SETPKTDEC);
k_sem_give(&context->tx_rx_sem);
return 0;
}
static void enc424j600_rx_thread(struct device *dev)
{
struct enc424j600_runtime *context = dev->driver_data;
u16_t eir;
u16_t estat;
u8_t counter;
while (true) {
k_sem_take(&context->int_sem, K_FOREVER);
enc424j600_clear_sfru(dev, ENC424J600_SFR3_EIEL,
ENC424J600_EIE_INTIE);
enc424j600_read_sfru(dev, ENC424J600_SFRX_EIRL, &eir);
enc424j600_read_sfru(dev, ENC424J600_SFRX_ESTATL, &estat);
LOG_DBG("ESTAT: 0x%04x", estat);
if (eir & ENC424J600_EIR_PKTIF) {
counter = (u8_t)estat;
while (counter) {
enc424j600_rx(dev);
enc424j600_read_sfru(dev,
ENC424J600_SFRX_ESTATL,
&estat);
counter = (u8_t)estat;
LOG_DBG("ESTAT: 0x%04x", estat);
}
goto done;
}
if (eir & ENC424J600_EIR_LINKIF) {
enc424j600_clear_sfru(dev, ENC424J600_SFRX_EIRL,
ENC424J600_EIR_LINKIF);
if (estat & ENC424J600_ESTAT_PHYLNK) {
LOG_INF("Link up");
enc424j600_setup_mac(dev);
} else {
LOG_INF("Link down");
}
goto done;
}
LOG_ERR("Unknown Interrupt, EIR: 0x%04x", eir);
done:
enc424j600_set_sfru(dev, ENC424J600_SFR3_EIEL,
ENC424J600_EIE_INTIE);
}
}
static enum ethernet_hw_caps enc424j600_get_capabilities(struct device *dev)
{
ARG_UNUSED(dev);
return ETHERNET_LINK_10BASE_T | ETHERNET_LINK_100BASE_T;
}
static void enc424j600_iface_init(struct net_if *iface)
{
struct device *dev = net_if_get_device(iface);
struct enc424j600_runtime *context = dev->driver_data;
net_if_set_link_addr(iface, context->mac_address,
sizeof(context->mac_address),
NET_LINK_ETHERNET);
context->iface = iface;
}
static int enc424j600_start_device(struct device *dev)
{
struct enc424j600_runtime *context = dev->driver_data;
u16_t tmp;
if (!context->suspended) {
LOG_INF("Not suspended");
return 0;
}
k_sem_take(&context->tx_rx_sem, K_FOREVER);
enc424j600_set_sfru(dev, ENC424J600_SFR3_ECON2L,
ENC424J600_ECON2_ETHEN |
ENC424J600_ECON2_STRCH);
enc424j600_read_phy(dev, ENC424J600_PSFR_PHCON1, &tmp);
tmp &= ~ENC424J600_PHCON1_PSLEEP;
enc424j600_write_phy(dev, ENC424J600_PSFR_PHCON1, tmp);
enc424j600_set_sfru(dev, ENC424J600_SFRX_ECON1L,
ENC424J600_ECON1_RXEN);
context->suspended = false;
k_sem_give(&context->tx_rx_sem);
LOG_INF("started");
return 0;
}
static int enc424j600_stop_device(struct device *dev)
{
struct enc424j600_runtime *context = dev->driver_data;
u16_t tmp;
if (context->suspended) {
LOG_WRN("Already suspended");
return 0;
}
k_sem_take(&context->tx_rx_sem, K_FOREVER);
enc424j600_clear_sfru(dev, ENC424J600_SFRX_ECON1L,
ENC424J600_ECON1_RXEN);
do {
k_sleep(10U);
enc424j600_read_sfru(dev, ENC424J600_SFRX_ESTATL, &tmp);
} while (tmp & ENC424J600_ESTAT_RXBUSY);
do {
k_sleep(10U);
enc424j600_read_sfru(dev, ENC424J600_SFRX_ECON1L, &tmp);
} while (tmp & ENC424J600_ECON1_TXRTS);
enc424j600_read_phy(dev, ENC424J600_PSFR_PHCON1, &tmp);
tmp |= ENC424J600_PHCON1_PSLEEP;
enc424j600_write_phy(dev, ENC424J600_PSFR_PHCON1, tmp);
enc424j600_clear_sfru(dev, ENC424J600_SFR3_ECON2L,
ENC424J600_ECON2_ETHEN |
ENC424J600_ECON2_STRCH);
context->suspended = true;
k_sem_give(&context->tx_rx_sem);
LOG_INF("stopped");
return 0;
}
static const struct ethernet_api api_funcs = {
.iface_api.init = enc424j600_iface_init,
.get_capabilities = enc424j600_get_capabilities,
.send = enc424j600_tx,
.start = enc424j600_start_device,
.stop = enc424j600_stop_device,
};
static int enc424j600_init(struct device *dev)
{
const struct enc424j600_config *config = dev->config->config_info;
struct enc424j600_runtime *context = dev->driver_data;
u8_t retries = ENC424J600_DEFAULT_NUMOF_RETRIES;
u16_t tmp;
/* SPI config */
context->spi_cfg.operation = SPI_WORD_SET(8);
context->spi_cfg.frequency = config->spi_freq;
context->spi_cfg.slave = config->spi_slave;
context->spi = device_get_binding((char *)config->spi_port);
if (!context->spi) {
LOG_ERR("SPI master port %s not found", config->spi_port);
return -EINVAL;
}
#ifdef CONFIG_ETH_ENC424J600_0_GPIO_SPI_CS
context->spi_cs.gpio_dev =
device_get_binding((char *)config->spi_cs_port);
if (!context->spi_cs.gpio_dev) {
LOG_ERR("SPI CS port %s not found", config->spi_cs_port);
return -EINVAL;
}
context->spi_cs.gpio_pin = config->spi_cs_pin;
context->spi_cfg.cs = &context->spi_cs;
#endif /* CONFIG_ETH_ENC424J600_0_GPIO_SPI_CS */
/* Initialize GPIO */
context->gpio = device_get_binding((char *)config->gpio_port);
if (!context->gpio) {
LOG_ERR("GPIO port %s not found", config->gpio_port);
return -EINVAL;
}
if (gpio_pin_configure(context->gpio, config->gpio_pin,
(GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE
| GPIO_INT_ACTIVE_LOW | GPIO_INT_DEBOUNCE))) {
LOG_ERR("Unable to configure GPIO pin %u",
config->gpio_pin);
return -EINVAL;
}
gpio_init_callback(&(context->gpio_cb), enc424j600_gpio_callback,
BIT(config->gpio_pin));
if (gpio_add_callback(context->gpio, &(context->gpio_cb))) {
return -EINVAL;
}
if (gpio_pin_enable_callback(context->gpio, config->gpio_pin)) {
return -EINVAL;
}
/* Check SPI connection */
do {
k_busy_wait(USEC_PER_MSEC * 1U);
enc424j600_write_sfru(dev, ENC424J600_SFRX_EUDASTL, 0x4AFE);
enc424j600_read_sfru(dev, ENC424J600_SFRX_EUDASTL, &tmp);
retries--;
} while (tmp != 0x4AFE && retries);
if (tmp != 0x4AFE) {
LOG_ERR("Timeout, failed to establish SPI connection");
return -EIO;
}
retries = ENC424J600_DEFAULT_NUMOF_RETRIES;
do {
k_busy_wait(USEC_PER_MSEC * 1U);
enc424j600_read_sfru(dev, ENC424J600_SFRX_ESTATL, &tmp);
retries--;
} while (!(tmp & ENC424J600_ESTAT_CLKRDY) && retries);
if (!(tmp & ENC424J600_ESTAT_CLKRDY)) {
LOG_ERR("CLKRDY not set");
return -EIO;
}
enc424j600_write_sbc(dev, ENC424J600_1BC_SETETHRST);
k_busy_wait(ENC424J600_PHY_READY_DELAY);
enc424j600_read_sfru(dev, ENC424J600_SFRX_EUDASTL, &tmp);
if (tmp) {
LOG_ERR("Failed to initialize ENC424J600");
return -EIO;
}
/* Configure TX and RX buffer */
enc424j600_write_sfru(dev, ENC424J600_SFR0_ETXSTL,
ENC424J600_TXSTART);
enc424j600_write_sfru(dev, ENC424J600_SFR0_ERXSTL,
ENC424J600_RXSTART);
enc424j600_write_sfru(dev, ENC424J600_SFR0_ERXTAILL,
(ENC424J600_RXEND - 1));
context->next_pkt_ptr = ENC424J600_RXSTART;
/* Disable user-defined buffer */
enc424j600_write_sfru(dev, ENC424J600_SFRX_EUDASTL,
(ENC424J600_RXEND - 1));
enc424j600_write_sfru(dev, ENC424J600_SFRX_EUDANDL,
(ENC424J600_RXEND - 1));
/* read MAC address byte 2 and 1 */
enc424j600_read_sfru(dev, ENC424J600_SFR3_MAADR1L, &tmp);
context->mac_address[0] = tmp;
context->mac_address[1] = tmp >> 8;
/* read MAC address byte 4 and 3 */
enc424j600_read_sfru(dev, ENC424J600_SFR3_MAADR2L, &tmp);
context->mac_address[2] = tmp;
context->mac_address[3] = tmp >> 8;
/* read MAC address byte 6 and 5 */
enc424j600_read_sfru(dev, ENC424J600_SFR3_MAADR3L, &tmp);
context->mac_address[4] = tmp;
context->mac_address[5] = tmp >> 8;
enc424j600_init_filters(dev);
enc424j600_init_phy(dev);
/* Setup interrupt logic */
enc424j600_set_sfru(dev, ENC424J600_SFR3_EIEL,
ENC424J600_EIE_PKTIE | ENC424J600_EIE_LINKIE);
if (CONFIG_ETHERNET_LOG_LEVEL == LOG_LEVEL_DBG) {
enc424j600_read_sfru(dev, ENC424J600_SFR3_EIEL, &tmp);
LOG_DBG("EIE: 0x%04x", tmp);
}
/* Enable Reception */
enc424j600_set_sfru(dev, ENC424J600_SFRX_ECON1L, ENC424J600_ECON1_RXEN);
if (CONFIG_ETHERNET_LOG_LEVEL == LOG_LEVEL_DBG) {
enc424j600_read_sfru(dev, ENC424J600_SFRX_ECON1L, &tmp);
LOG_DBG("ECON1: 0x%04x", tmp);
}
/* Start interruption-poll thread */
k_thread_create(&context->thread, context->thread_stack,
CONFIG_ETH_ENC424J600_RX_THREAD_STACK_SIZE,
(k_thread_entry_t)enc424j600_rx_thread,
(void *)dev, NULL, NULL,
K_PRIO_COOP(CONFIG_ETH_ENC424J600_RX_THREAD_PRIO),
0, K_NO_WAIT);
enc424j600_set_sfru(dev, ENC424J600_SFR3_EIEL,
ENC424J600_EIE_INTIE);
context->suspended = false;
LOG_INF("ENC424J600 Initialized");
return 0;
}
static struct enc424j600_runtime enc424j600_0_runtime = {
.tx_rx_sem = Z_SEM_INITIALIZER(enc424j600_0_runtime.tx_rx_sem,
1, UINT_MAX),
.int_sem = Z_SEM_INITIALIZER(enc424j600_0_runtime.int_sem,
0, UINT_MAX),
};
static const struct enc424j600_config enc424j600_0_config = {
.gpio_port = DT_INST_0_MICROCHIP_ENC424J600_INT_GPIOS_CONTROLLER,
.gpio_pin = DT_INST_0_MICROCHIP_ENC424J600_INT_GPIOS_PIN,
.spi_port = DT_INST_0_MICROCHIP_ENC424J600_BUS_NAME,
.spi_freq = DT_INST_0_MICROCHIP_ENC424J600_SPI_MAX_FREQUENCY,
.spi_slave = DT_INST_0_MICROCHIP_ENC424J600_BASE_ADDRESS,
#ifdef CONFIG_ETH_ENC424J600_0_GPIO_SPI_CS
.spi_cs_port = DT_INST_0_MICROCHIP_ENC424J600_CS_GPIOS_CONTROLLER,
.spi_cs_pin = DT_INST_0_MICROCHIP_ENC424J600_CS_GPIOS_PIN,
#endif /* CONFIG_ETH_ENC424J600_0_GPIO_SPI_CS */
.timeout = CONFIG_ETH_ENC424J600_TIMEOUT,
};
ETH_NET_DEVICE_INIT(enc424j600_0, DT_INST_0_MICROCHIP_ENC424J600_LABEL,
enc424j600_init, &enc424j600_0_runtime,
&enc424j600_0_config, CONFIG_ETH_INIT_PRIORITY, &api_funcs,
NET_ETH_MTU);

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/* ENC424J600 Stand-alone Ethernet Controller with SPI
*
* Copyright (c) 2016 Intel Corporation
* Copyright (c) 2019 PHYTEC Messtechnik GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <kernel.h>
#include <drivers/gpio.h>
#ifndef _ENC424J600_
#define _ENC424J600_
/* Bank 0 Registers */
#define ENC424J600_SFR0_ETXSTL 0x00
#define ENC424J600_SFR0_ETXSTH 0x01
#define ENC424J600_SFR0_ETXLENL 0x02
#define ENC424J600_SFR0_ETXLENH 0x03
#define ENC424J600_SFR0_ERXSTL 0x04
#define ENC424J600_SFR0_ERXSTH 0x05
#define ENC424J600_SFR0_ERXTAILL 0x06
#define ENC424J600_SFR0_ERXTAILH 0x07
#define ENC424J600_SFR0_ERXHEADL 0x08
#define ENC424J600_SFR0_ERXHEADH 0x09
#define ENC424J600_SFR0_EDMASTL 0x0A
#define ENC424J600_SFR0_EDMASTH 0x0B
#define ENC424J600_SFR0_EDMALENL 0x0C
#define ENC424J600_SFR0_EDMALENH 0x0D
#define ENC424J600_SFR0_EDMADSTL 0x0E
#define ENC424J600_SFR0_EDMADSTH 0x0F
#define ENC424J600_SFR0_EDMACSL 0x10
#define ENC424J600_SFR0_EDMACSH 0x11
#define ENC424J600_SFR0_ETXSTATL 0x12
#define ENC424J600_SFR0_ETXSTATH 0x13
#define ENC424J600_SFR0_ETXWIREL 0x14
#define ENC424J600_SFR0_ETXWIREH 0x15
/* Common Registers */
#define ENC424J600_SFRX_EUDASTL 0x16
#define ENC424J600_SFRX_EUDASTH 0x17
#define ENC424J600_SFRX_EUDANDL 0x18
#define ENC424J600_SFRX_EUDANDH 0x19
#define ENC424J600_SFRX_ESTATL 0x1A
#define ENC424J600_SFRX_ESTATH 0x1B
#define ENC424J600_SFRX_EIRL 0x1C
#define ENC424J600_SFRX_EIRH 0x1D
#define ENC424J600_SFRX_ECON1L 0x1E
#define ENC424J600_SFRX_ECON1H 0x1F
/* Bank 1 Registers */
#define ENC424J600_SFR1_EHT1L 0x20
#define ENC424J600_SFR1_EHT1H 0x21
#define ENC424J600_SFR1_EHT2L 0x22
#define ENC424J600_SFR1_EHT2H 0x23
#define ENC424J600_SFR1_EHT3L 0x24
#define ENC424J600_SFR1_EHT3H 0x25
#define ENC424J600_SFR1_EHT4L 0x26
#define ENC424J600_SFR1_EHT4H 0x27
#define ENC424J600_SFR1_EPMM1L 0x28
#define ENC424J600_SFR1_EPMM1H 0x29
#define ENC424J600_SFR1_EPMM2L 0x2A
#define ENC424J600_SFR1_EPMM2H 0x2B
#define ENC424J600_SFR1_EPMM3L 0x2C
#define ENC424J600_SFR1_EPMM3H 0x2D
#define ENC424J600_SFR1_EPMM4L 0x2E
#define ENC424J600_SFR1_EPMM4H 0x2F
#define ENC424J600_SFR1_EPMCSL 0x30
#define ENC424J600_SFR1_EPMCSH 0x31
#define ENC424J600_SFR1_EPMOL 0x32
#define ENC424J600_SFR1_EPMOH 0x33
#define ENC424J600_SFR1_ERXFCONL 0x34
#define ENC424J600_SFR1_ERXFCONH 0x35
/* Bank 2 Registers */
#define ENC424J600_SFR2_MACON1L 0x40
#define ENC424J600_SFR2_MACON1H 0x41
#define ENC424J600_SFR2_MACON2L 0x42
#define ENC424J600_SFR2_MACON2H 0x43
#define ENC424J600_SFR2_MABBIPGL 0x44
#define ENC424J600_SFR2_MABBIPGH 0x45
#define ENC424J600_SFR2_MAIPGL 0x46
#define ENC424J600_SFR2_MAIPGH 0x47
#define ENC424J600_SFR2_MACLCONL 0x48
#define ENC424J600_SFR2_MACLCONH 0x49
#define ENC424J600_SFR2_MAMXFLL 0x4A
#define ENC424J600_SFR2_MAMXFLH 0x4B
#define ENC424J600_SFR2_MICMDL 0x52
#define ENC424J600_SFR2_MICMDH 0x53
#define ENC424J600_SFR2_MIREGADRL 0x54
#define ENC424J600_SFR2_MIREGADRH 0x55
/* Bank 3 Registers */
#define ENC424J600_SFR3_MAADR3L 0x60
#define ENC424J600_SFR3_MAADR3H 0x61
#define ENC424J600_SFR3_MAADR2L 0x62
#define ENC424J600_SFR3_MAADR2H 0x63
#define ENC424J600_SFR3_MAADR1L 0x64
#define ENC424J600_SFR3_MAADR1H 0x65
#define ENC424J600_SFR3_MIWRL 0x66
#define ENC424J600_SFR3_MIWRH 0x67
#define ENC424J600_SFR3_MIRDL 0x68
#define ENC424J600_SFR3_MIRDH 0x69
#define ENC424J600_SFR3_MISTATL 0x6A
#define ENC424J600_SFR3_MISTATH 0x6B
#define ENC424J600_SFR3_EPAUSL 0x6C
#define ENC424J600_SFR3_EPAUSH 0x6D
#define ENC424J600_SFR3_ECON2L 0x6E
#define ENC424J600_SFR3_ECON2H 0x6F
#define ENC424J600_SFR3_ERXWML 0x70
#define ENC424J600_SFR3_ERXWMH 0x71
#define ENC424J600_SFR3_EIEL 0x72
#define ENC424J600_SFR3_EIEH 0x73
#define ENC424J600_SFR3_EIDLEDL 0x74
#define ENC424J600_SFR3_EIDLEDH 0x75
/* Unbanked SFRs */
#define ENC424J600_SFR4_EGPDATA 0x80
#define ENC424J600_SFR4_ERXDATA 0x82
#define ENC424J600_SFR4_EUDADATA 0x84
#define ENC424J600_SFR4_EGPRDPTL 0x86
#define ENC424J600_SFR4_EGPRDPTH 0x87
#define ENC424J600_SFR4_EGPWRPTL 0x88
#define ENC424J600_SFR4_EGPWRPTH 0x89
#define ENC424J600_SFR4_ERXRDPTL 0x8A
#define ENC424J600_SFR4_ERXRDPTH 0x8B
#define ENC424J600_SFR4_ERXWRPTL 0x8C
#define ENC424J600_SFR4_ERXWRPTH 0x8D
#define ENC424J600_SFR4_EUDARDPTL 0x8E
#define ENC424J600_SFR4_EUDARDPTH 0x8F
#define ENC424J600_SFR4_EUDAWRPTL 0x90
#define ENC424J600_SFR4_EUDAWRPTH 0x91
/* PHY Registers */
#define ENC424J600_PSFR_PHCON1 (BIT(8) | 0x00)
#define ENC424J600_PSFR_PHSTAT1 (BIT(8) | 0x01)
#define ENC424J600_PSFR_PHANA (BIT(8) | 0x04)
#define ENC424J600_PSFR_PHANLPA (BIT(8) | 0x05)
#define ENC424J600_PSFR_PHANE (BIT(8) | 0x06)
#define ENC424J600_PSFR_PHCON2 (BIT(8) | 0x11)
#define ENC424J600_PSFR_PHSTAT2 (BIT(8) | 0x1B)
#define ENC424J600_PSFR_PHSTAT3 (BIT(8) | 0x1F)
/* SPI Instructions */
#define ENC424J600_1BC_B0SEL 0xC0
#define ENC424J600_1BC_B1SEL 0xC2
#define ENC424J600_1BC_B2SEL 0xC4
#define ENC424J600_1BC_B3SEL 0xC6
#define ENC424J600_1BC_SETETHRST 0xCA
#define ENC424J600_1BC_FCDISABLE 0xE0
#define ENC424J600_1BC_FCSINGLE 0xE2
#define ENC424J600_1BC_FCMULTIPLE 0xE4
#define ENC424J600_1BC_FCCLEAR 0xE6
#define ENC424J600_1BC_SETPKTDEC 0xCC
#define ENC424J600_1BC_DMASTOP 0xD2
#define ENC424J600_1BC_DMACKSUM 0xD8
#define ENC424J600_1BC_DMACKSUMS 0xDA
#define ENC424J600_1BC_DMACOPY 0xDC
#define ENC424J600_1BC_DMACOPYS 0xDE
#define ENC424J600_1BC_SETTXRTS 0xD4
#define ENC424J600_1BC_ENABLERX 0xE8
#define ENC424J600_1BC_DISABLERX 0xEA
#define ENC424J600_1BC_SETEIE 0xEC
#define ENC424J600_1BC_CLREIE 0xEE
#define ENC424J600_2BC_RBSEL 0xC8
#define ENC424J600_3BC_WGPRDPT 0x60
#define ENC424J600_3BC_RGPRDPT 0x62
#define ENC424J600_3BC_WRXRDPT 0x64
#define ENC424J600_3BC_RRXRDPT 0x66
#define ENC424J600_3BC_WUDARDPT 0x68
#define ENC424J600_3BC_RUDARDPT 0x6A
#define ENC424J600_3BC_WGPWRPT 0x6C
#define ENC424J600_3BC_RGPWRPT 0x6E
#define ENC424J600_3BC_WRXWRPT 0x70
#define ENC424J600_3BC_RRXWRPT 0x72
#define ENC424J600_3BC_WUDAWRPT 0x74
#define ENC424J600_3BC_RUDAWRPT 0x76
#define ENC424J600_NBC_RCR 0x00
#define ENC424J600_NBC_WCR 0x40
#define ENC424J600_NBC_RCRU 0x20
#define ENC424J600_NBC_WCRU 0x22
#define ENC424J600_NBC_BFS 0x80
#define ENC424J600_NBC_BFC 0xA0
#define ENC424J600_NBC_BFSU 0x24
#define ENC424J600_NBC_BFCU 0x26
#define ENC424J600_NBC_RGPDATA 0x28
#define ENC424J600_NBC_WGPDATA 0x2A
#define ENC424J600_NBC_RRXDATA 0x2C
#define ENC424J600_NBC_WRXDATA 0x2E
#define ENC424J600_NBC_RUDADATA 0x30
#define ENC424J600_NBC_WUDADATA 0x32
/* Significant bits */
#define ENC424J600_MICMD_MIIRD BIT(0)
#define ENC424J600_MISTAT_BUSY BIT(0)
#define ENC424J600_ESTAT_RXBUSY BIT(13)
#define ENC424J600_ESTAT_CLKRDY BIT(12)
#define ENC424J600_ESTAT_PHYLNK BIT(8)
#define ENC424J600_MACON2_FULDPX BIT(0)
#define ENC424J600_ERXFCON_CRCEN BIT(6)
#define ENC424J600_ERXFCON_RUNTEEN BIT(5)
#define ENC424J600_ERXFCON_RUNTEN BIT(4)
#define ENC424J600_ERXFCON_UCEN BIT(3)
#define ENC424J600_ERXFCON_NOTMEEN BIT(2)
#define ENC424J600_ERXFCON_MCEN BIT(1)
#define ENC424J600_ERXFCON_BCEN BIT(0)
#define ENC424J600_PHANA_ADNP BIT(15)
#define ENC424J600_PHANA_ADFAULT BIT(13)
#define ENC424J600_PHANA_ADPAUS_SYMMETRIC_ONLY BIT(10)
#define ENC424J600_PHANA_AD100FD BIT(8)
#define ENC424J600_PHANA_AD100 BIT(7)
#define ENC424J600_PHANA_AD10FD BIT(6)
#define ENC424J600_PHANA_AD10 BIT(5)
#define ENC424J600_PHANA_ADIEEE_DEFAULT BIT(0)
#define ENC424J600_EIE_INTIE BIT(15)
#define ENC424J600_EIE_MODEXIE BIT(14)
#define ENC424J600_EIE_HASHIE BIT(13)
#define ENC424J600_EIE_AESIE BIT(12)
#define ENC424J600_EIE_LINKIE BIT(11)
#define ENC424J600_EIE_PKTIE BIT(6)
#define ENC424J600_EIE_DMAIE BIT(5)
#define ENC424J600_EIE_TXIE BIT(3)
#define ENC424J600_EIE_TXABTIE BIT(2)
#define ENC424J600_EIE_RXABTIE BIT(1)
#define ENC424J600_EIE_PCFULIE BIT(0)
#define ENC424J600_ECON1_PKTDEC BIT(8)
#define ENC424J600_ECON1_TXRTS BIT(1)
#define ENC424J600_ECON1_RXEN BIT(0)
#define ENC424J600_ECON2_ETHEN BIT(15)
#define ENC424J600_ECON2_STRCH BIT(14)
#define ENC424J600_EIR_LINKIF BIT(11)
#define ENC424J600_EIR_PKTIF BIT(6)
#define ENC424J600_EIR_TXIF BIT(3)
#define ENC424J600_EIR_TXABTIF BIT(2)
#define ENC424J600_EIR_RXABTIF BIT(1)
#define ENC424J600_EIR_PCFULIF BIT(0)
#define ENC424J600_PHCON1_PSLEEP BIT(11)
#define ENC424J600_PHCON1_RENEG BIT(9)
#define ENC424J600_PHSTAT3_SPDDPX_FD BIT(4)
#define ENC424J600_PHSTAT3_SPDDPX_100 BIT(3)
#define ENC424J600_PHSTAT3_SPDDPX_10 BIT(2)
/* Buffer Configuration */
#define ENC424J600_TXSTART 0x0000U
#define ENC424J600_TXEND 0x2FFFU
#define ENC424J600_RXSTART (ENC424J600_TXEND + 1)
#define ENC424J600_RXEND 0x5FFFU
#define ENC424J600_EUDAST_DEFAULT 0x6000U
#define ENC424J600_EUDAND_DEFAULT (ENC424J600_EUDAST + 1)
/* Status vectors array size */
#define ENC424J600_RSV_SIZE 6U
#define ENC424J600_PTR_NXP_PKT_SIZE 2U
/* Full-Duplex mode Inter-Packet Gap default value */
#define ENC424J600_MABBIPG_DEFAULT 0x15U
#define ENC424J600_DEFAULT_NUMOF_RETRIES 3U
/* Delay for PHY write/read operations (25.6 us) */
#define ENC424J600_PHY_ACCESS_DELAY 26U
#define ENC424J600_PHY_READY_DELAY 260U
struct enc424j600_config {
const char *gpio_port;
u8_t gpio_pin;
const char *spi_port;
u8_t spi_cs_pin;
const char *spi_cs_port;
u32_t spi_freq;
u8_t spi_slave;
u8_t full_duplex;
s32_t timeout;
};
struct enc424j600_runtime {
struct net_if *iface;
K_THREAD_STACK_MEMBER(thread_stack,
CONFIG_ETH_ENC424J600_RX_THREAD_STACK_SIZE);
struct k_thread thread;
u8_t mac_address[6];
struct device *gpio;
struct device *spi;
struct spi_cs_control spi_cs;
struct spi_config spi_cfg;
struct gpio_callback gpio_cb;
struct k_sem tx_rx_sem;
struct k_sem int_sem;
u16_t next_pkt_ptr;
bool suspended;
};
#endif /*_ENC424J600_*/

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# Copyright (c) 2019, Phytec Messtechnik GmbH
# SPDX-License-Identifier: Apache-2.0
title: 100Base-T Ethernet Controller with SPI Interface
description: >
This binding gives a base representation of the ENC424J600 Stand-Alone
Ethernet Controller
compatible: "microchip,enc424j600"
include: [spi-device.yaml, ethernet.yaml]
properties:
int-gpios:
type: phandle-array
required: true