Enables using the whole flash on CH32V208
This also involves limiting frequency of the CPU to 120Mhz
from 144Mhz to meet recommendations.
Signed-off-by: Camille BAUD <mail@massdriver.space>
The CH32V006 is part of the CH32V00x series of 32 bit RISC-V
microcontrollers. This series is an evolution of the CH32V003 which
was used as a basis for this Devicetree definition.
Compared to the CH32V003, thie CH32V006 has an extra GPIO port (PB),
an extra UART (UART2), 8 KiB of RAM, 62 KiB of flash, and uses the
QingKe V2C core.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Change the base address of GPIO and pinctrl voltage selection
The new base address enables more pins to support voltage selection.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The GPTM is a general purpose module with a 16 bit prescaler, 16 bit
counter, and 4 compare units that can be used for PWM generation.
Use the same style as gd32 where the timer is a counter and the PWM
mode is a child node.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The Alternate Function IO (AFIO) block must have the clock enabled
before configuring. Some remappings seem to work without, but some
like EXTI do not. Fix.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Implement the functions of I2C host and target.
I2CM: supports nine hosts and each one able located at I2C interface
0~12.
supports two 32 bytes dedicated FIFO mode for read and write.
I2CS: supports three targets and each one able located at I2C
interface 0~8.
supports 16 bytes dedicated FIFO mode that only supports write or
read mode and the maximum buffer size is 256 bytes.
support non-FIFO write to shared FIFO read mode. The maximum
shared FIFO size for read is 256 bytes.
The APIs test include: i2c_write(), i2c_read(), i2c_burst_read(),
i2c_burst_write(), i2c_write_read()
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The CH32V003 CPU is a QingKe V2A while others in the CH32V00x series
use the QingKe V2C. Prepare for adding support for the CH32V006 moving
to the more specifc qingke-v2a, moving some cases of SOC_CH32V003
actually meaning SOC_FAMILY_QINGKE_V2A.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Add Bouffalo Lab serial driver. The driver uses pinctrl to configure
pins and have power management capabilities.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add it515xx analog to digital converter driver which supports 8 channels
ch0 ~ ch7 and 12-bit resolution.
Signed-off-by: Yunshao Chiang <Yunshao.Chiang@ite.com.tw>
The device tree entry for cva6 is currently missing a device tree node
for the mtime and mtimecmp registers in the core-local interrupt
controllers.
This causes the RISC-V machine timer driver not to be built, causing
build failures as the system clock is missing.
This commit rectifies this by adding the corresponding device tree
entry.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
Adds support for the CVA6 family of RISC-V CPUs.
CVA6 is commonly found as a soft core CPU on FPGA designs.
Different configurations and instruction set extensions can be
configured, and different SoCs targeting various FPGA boards are
available.
This commit adds support for the 32-bit and 64-bit configurations
of CVA6, as well as three slightly different SoCs (a minimal 32-bit
configuration, a 64-bit configuration without FPU, a 64-bit
configuration with FPU).
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The IT8xxx2 timer driver uses timer 7 and timer 8 to implement the alarm
timer and the top timer, respectively.
Signed-off-by: Yunshao Chiang <Yunshao.Chiang@ite.com.tw>
Use vendor prefix "neorv32" for all peripherals provided by the NEORV32
RISV-V Processor project.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This patch adds an initial driver for the WCH DMA
controller. All hardware features and most interface
features are implemented.
Signed-off-by: Paul Wedeck <paulwedeck@gmail.com>
