* Replace copies of fixed-partitions nodes in related boards by
referencing the apropriate partition table from the available list.
* For better reference the `partitions_*.dtsi` file has boot offset,
purpose and the flash size encoded in the file name. Default flash size
is considered to be 4MB.
* Added the flash size node for the boards which are not based on the
module.
* Removed flash size registry from the esp32.*common.dtsi
Signed-off-by: Marek Matej <marek.matej@espressif.com>
These two new ICs are variants of the nRF54L15 with different memory
sizes:
- nRF54L05: 500KB RRAM, 96KB RAM
- nRF54L10: 1022KB RRAM, 192KB RAM
- nRF54L15: 1524KB RRAM, 256KB RAM
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add `hifive_unmatched//s7` (earlier selected by default, using
`hifive_unmatched`) and `hifive_unmatched//u74` targets.
Define work-area for other 4 cores in openocd.cfg
Update twister platform white/black lists, to support new targets
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Add `hifive_unleashed//e51` (earlier selected by default, using
`hifive_unleashed`) and `hifive_unleashed//u54` targets.
Define work-area for other 4 cores in openocd.cfg
Update twister platform white/black lists, to support new targets
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adjusts the sizes of the two PLIC nodes AE350 defines:
* `plic0` size is changed from `0x04000000` to `0x02000000`
* `plic_sw` size is changed from `0x04000000` to `0x00400000`
Without these change, `plic0` address space would overlap with `plic_sw`,
and with other memory-mapped peripherals.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Renamed andestech,plic-sw to andestech,mbox-plic-sw because the mbox node
is based on the PLIC interrupt controller node instead using the plic
hardware directly.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The plic-sw is the same hardware as the plic interrupt contoller and should
be used with intc_plic driver instead of separate mbox driver.
Renamed plic-sw node from "mbox: mbox-controller@e6400000" to
"plic_sw: interrupt-controller@e6400000".
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The production version of the nRF54L15 SoC is now available, so remove
the initial Engineering A (EngA) preview version.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add board support for eval board ganymed_bob, which
is a break-out-board for both soc variants.
Variants of the soc are GBM and GEN1.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
I2S driver was merged after interrupt .dtsi was changed,
causing CI to fail. This updates it accordingly.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add definition of the nRF9280 SiP with its Application,
Radio, and Peripheral Processor (PPR) cores and a basic set
of peripherals: GRTC, GPIOs, GPIOTE, and UARTs and few others.
Signed-off-by: Emanuele Di Santo <emdi@nordicsemi.no>
Co-authored-by: Andreas Moltumyr <andreas.moltumyr@nordicsemi.no>
Device tree configuration for USB serial node and clock control
fix for proper device initialization.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Between SoC revisions, the address was moved from 0x5F909000 in the
global domain, to 0xF0000000 in PPR's private address space.
Move the corresponding DT node out of `cpuppr_vpr` range to a separate
bus node, which is considered inaccessible to all cores but `cpuppr`.
This is expressed by selectively leaving out the `simple-bus` compatible
and `ranges` property, i.e., they're only set in `nrf54h20_cpuppr.dtsi`.
This lets the interrupt controller node remain visible at system level,
for the purpose of describing IRQ mappings between cores in devicetree.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Rename it from litex,eth to litex,liteeth
to reflect the new name of the driver.
Zero got removed from the litex
ethernet compatible, as it now supports
multiple instances.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
remove litex,sys-clock-frequency from litex,clk,
because we already define that in the clock-frequency of cpu0.
This can be accessed via
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
According to the RV32M1 Series Manual, Rev 1.1 RV32M1 series supports the C
extension, and doesn't support the A extension. Apply fixes accordingly.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
After changing the VEVIF and BELLBOARD names,
the dts for the individual boards must be aligned.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Kconfig, .ld and comments fixing
Fixed address of UART1, WDT and RTC timer disabled by default
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Update the native controller to the new HCI driver API. The devicetree
node is placed under existing `radio` nodes, which seemed like the most
intuitive option.
Signed-off-by: Johan Hedberg <johan.hedberg@gmail.com>
