Disable the I2C1 node in the CH32V003 SoC devicetree.
Boards which use I2C1 should enable it explicitly in their board devicetree
or overlay. This keeps the SoC dtsi from enabling unused devices by
default.
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ find dts/riscv/ -type f \
-exec ./scripts/check_quoted_includes.py -w {} \;
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Extend the esp32 lp_uart driver to the esp32c5 and esp32p4. On the
esp32p4 the LP UART signals are routed through the LP GPIO matrix and
the controller is clocked from the precise XTAL_D2 source instead of
the uncalibrated RC_FAST, so the baud-rate framing is reliable.
Relax the fixed-pin bindings, describe the lp_uart node pins on the
c5/c6/p4 HP and LP cores, and extend the echo_ulp sample. Update
hal_espressif for the esp32p4 LP GPIO matrix and clock-tree helpers.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
align the devicetree structure
with the recently added more generic
Synopsys ethernet driver, as the esp32
also uses the same IP from Synopsys, so we
can add support for the esp32 in that driver
easier.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The ESP32-C5 has TWAI-FD capable controllers that support both
Classic CAN and CAN-FD frames. Update the SoC dtsi to use the new
espressif,esp32-twaifd compatible so the new TWAI-FD driver binds with
it.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add single-core and SMP RISC-V AIA APLIC+IMSIC board variants as
nested variants of the qemu_virt_riscv32 SoC, mirroring the
qemu_riscv64 'smode' variant precedent.
The APLIC+IMSIC variants:
qemu_riscv32/qemu_virt_riscv32/aia-imsic
qemu_riscv32/qemu_virt_riscv32/aia-imsic/smp
These variants select a common APLIC topology include and add the IMSIC
nodes and properties needed for MSI delivery. They override the per-cpu
riscv,isa-extensions list to advertise smcsrind, which the RISC-V
indirect-CSR (Smcsrind) extension uses to access AIA external-interrupt
CSRs.
The board Kconfig selects RISCV_HAS_AIA on the APLIC+IMSIC variants,
which flips the SoC-level PLIC default off (see the prior commit). The
QEMU command line gates -machine virt,aia=aplic-imsic on the same flag.
The bare qemu_riscv32 identifier is preserved unchanged so existing
downstream platform_allow entries keep resolving.
The APLIC+IMSIC variant yamls intentionally do not set
testing.default=true: interrupt-driven UART through APLIC+IMSIC is not
yet routed for the generic shell/perf/pytest samples, so leaving them as
default would schedule those samples onto a target where they cannot
reach the shell prompt. Tests that explicitly cover the AIA path opt in
via platform_allow / integration_platforms.
Signed-off-by: Afonso Oliveira <afonso.oliveira707@gmail.com>
Assisted-by: Codex:GPT-5.5
Assisted-by: Claude:Fable-5
Move the PLIC node and PLIC-specific interrupt wiring out of the shared
virt-riscv include.
Add them to a QEMU PLIC topology include used by the board files that
still use PLIC. This leaves the shared QEMU virt include interrupt
controller neutral, so AIA variants can select their own topology without
deleting or overriding inherited PLIC nodes and interrupt maps.
Signed-off-by: Afonso Oliveira <afonso.oliveira707@gmail.com>
Assisted-by: Codex:GPT-5.5
Add and modify nodes to feature the new SF controller
Update boards to use the new controller,
significantly increase performance for a lot of them
Allow effectively truly representing the flash,
Allow setting the flash offset via ranges
use ranges properly
Signed-off-by: Camille BAUD <mail@massdriver.space>
Handle necessary code relocation better,
clearly delimiting what is required and what is not
Also group RAM together
Signed-off-by: Camille BAUD <mail@massdriver.space>
The QingKe V2A, V2C, and V4C have a Debug Module with two data
registers `data0` and `data1`. These can be used with SDI compatible
debuggers such as `minichlink` to send console data to the host.
Add a console driver communicates with the host and fails gracefully
if the driver is enabled but the debugger is not connected.
Compared to the UART console, the debug console uses 916 bytes less
flash and frees up a UART.
Tested on the ch32v006evt and bluepillplus_ch32v203. To test, add
`&sdiconsole { status = "okay"; };` to the board Devicetree, set
`zephyr,console = &sdiconsole`, and enable the driver.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The flash on the ch32v series starts at 0x8000000 and, depending on
the system configuration, is aliased to 0x0. When the ch32v003 support
was first submitted, `minichlink` would accept either the real or the
alised address, but became stricter sometime in the last two years.
Fix the base address in the ch32v00{3,6}.dtsi, change
`minichlink.py` to always use the flash address from the build
configuration, and remove the `--dt-flash=y` work-arounds from the
more recent board configurations.
Tested by building `hello_world` for `ch32v003evt`, `ch32v006evt`,
`bluepillplus_ch32v203`, `ch32v303vct6_evt`, and `ch32v307v_evt_r1`;
running `west -v flash` and checking the command uses `0x8000000`.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Utilize the RAM allocation for nrf7120 tf-m application. Move RAM
macros ram00_sram, ram01_sram, ram02_sram and ram03_sram under
cpuapp_sram for application to use the whole RAM space. Secure RAM
will use 128 Kb while NS ram use 888 Kb out from 1016 Kb from the
total memory size.
Note that ram02_sram and ram03_sram is under AMBIX03 bus and it will
take one more cycle for Appcore to access it from AMBIX00 -> AMBIX03.
Heap allocation of zephyr application normally allocate heap from the
end of address and grow downward. Application that requires lower
latency should prevent usage of RAM02, RAM03, they need
to define overlay file themselves.
Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
Wires interrupt routing for the ElemRV-N board: configures the
PLIC with 7 interrupt sources (riscv,ndev = <7>), routes GPIO0 to
PLIC IRQ 1 (priority 1) and UART0 to PLIC IRQ 5 (priority 1) in
the platform DTSI.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Adds a sifive,plic-1.0.0 PLIC node to the Nitrogen platform DTSI,
mapped at 0xf0800000 (64 MiB region), connected to
HLIC M-mode (IRQ 11) and S-mode (IRQ 9) external interrupt lines,
with up to 7 priority levels.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Add the device tree for the ESP32-P4 SoC: HP-core peripherals
(cpu, intc, gpio, uart, i2c, spi, dma, ledc, etc.), LP-core
memory regions, on-chip LDO regulator node and the LP-core
specific dtsi.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add CPU PLL initialization, configuration, and clock gating for BL808.
The CPUPLL uses the same WAC PLL register layout as AUPLL, located at
CCI_BASE + 0x7D0 with CCI_CPUPLL_* field prefixes.
Config tables provide per-crystal analog parameters and SDMIN values
for the 480 MHz reference frequency. CPUPLL is the default root clock
source in bl808.dtsi at 320 MHz, with BCLK at 80 MHz. Boards can
override up to 480 MHz via DTS overlay.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add Audio PLL initialization, configuration, and clock gating to the
BL808 clock controller. The AUPLL uses the CCI register block at
offset 0x750 with the same WAC PLL layout as WIFIPLL.
Config tables provide per-crystal analog parameters and SDMIN values
targeting 442.368 MHz (48 kHz audio family). BFLB_MUL_CLK scales to
other frequencies such as 451.584 MHz for the 44.1 kHz family.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Select CPU_HAS_DCACHE on ESP32-S2, S3 and C5 and auto-enable
CACHE_MANAGEMENT in each defconfig when ESP_SPIRAM is selected.
This activates the cache_esp32 driver where it is useful, so
portable sys_cache_data_* calls keep PSRAM and DMA buffers
coherent.
The L1 dcache line size is declared via the cpu@0 devicetree
node so the generic DCACHE_LINE_SIZE Kconfig default picks it
up automatically. SoCs without writeback cache (ESP32, C2, C3,
C6 and H2) are left untouched.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Currently there are a handful of inconsistencies between DTS for SOCs
in this series. Adds a new common peripheral file with /delete-node/
used to remove inactive peripherals.
Signed-off-by: James Bennion-Pedley <james@bojit.org>
The RTC hardware is compatible with the it82xx2 series, so it reuses
the same compatible and driver implementation.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Implement AUPLL management in the BL61x clock control driver,
following the same pattern as the existing WIFIPLL implementation.
Signed-off-by: William Markezana <william.markezana@gmail.com>
The tsen (Thermal Sensor) and bt-hci (Bluetooth) nodes do not use standard
memory-mapped registers, so they do not have 'reg' properties. Because they
were placed inside the /soc node (which is a simple-bus), the Devicetree
compiler threw 'simple_bus_reg' warnings during compilation.
This commit moves these logical/blob-controlled nodes to the root level
to comply with Devicetree specifications and clear the compiler warnings
for all bflb family SoCs.
Fixes#108714
Signed-off-by: T Madhusudhan Rao <tetakalam@aerlync.com>
Disable GPIO interrupts for the nRF54H20 FLPR core,
as it doesn't support GPIO interrupts by design.
Signed-off-by: Paweł Pelikan <pawel.pelikan@nordicsemi.no>
Enable the on-chip BLE controller on BL60x boards (bl604e_iot_dvk,
ai_wb2_12f_kit): include bl60x_em_8kb.dtsi to reduce sram0 to 168 KB
(8 KB exchange memory carved from the top of SRAM, GLB_EM_SEL=3),
add zephyr,bt-hci chosen, and activate the bt-hci and TRNG nodes.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add bt-hci node to bl61x.dtsi using the shared bflb,bt-hci binding.
Add exchange memory overlays for 32 KB and 64 KB configurations
that reduce WRAM available to the application when BLE is enabled.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add a Supervisor-mode board variant for the QEMU RISC-V 64-bit virt
machine so twister exercises S-mode in CI.
Configure board.cmake to append s=on,u=on,pmp=on,priv_spec=v1.12.0,
sv39=on when CONFIG_RISCV_S_MODE is set, using string(APPEND) consistent
with the CONFIG_RISCV_PMP flag handling.
Three flags are required for compatibility with the rv64i bare CPU in
QEMU 10 (shipped with the Zephyr SDK):
- sv39=on instead of mmu=on: QEMU 10 separates MMU hardware presence
from the satp addressing mode; without an explicit mode QEMU defaults
to bare and virtual addressing is disabled.
- pmp=on: the rv64i bare CPU has no PMP by default; reset.S writes PMP
CSRs unconditionally, causing an illegal-instruction trap before UART
is initialised if PMP support is absent.
- zicntr=on: QEMU 10 separates Zicntr from the base I extension; without
it csrr time traps with mcause=2 in the M-mode SBI timer handler.
Set riscv,privilege-modes = "m", "s", "u" on all cpu nodes in the
S-mode devicetree overlay so all harts correctly describe Supervisor-mode
support on SMP systems. Simplify the privilege-modes binding wording to
avoid implying that only M-mode is assumed when the property is absent.
Exclude tests incompatible with S-mode: semihosting (requires M-mode
firmware), shared-interrupt tests (only one software-triggerable IRQ in
S-mode), and the RISC-V ISR table tests (timer IRQ already claimed).
Signed-off-by: Alexios Lyrakis <alexios.lyrakis@gmail.com>
Add supports for XIAO ESP32C5, a compact development board based on the
ESP32-C5 SoC.
Assisted-by: Cursor:composer-2
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add a die temperature sensor driver for Bouffalo Lab SoCs using
the internal TSEN peripheral integrated into the GPADC.
The driver uses the ADC subsystem for hardware initialization and
raw sample acquisition via adc_bflb_tsen_read_phase(). Temperature
is computed from two ADC measurement phases (TSVBE_LOW toggle)
using the formula: temp = (|v0 - v1| - tsen_offset) / 7.753
The TSEN calibration offset is read from efuse when available,
falling back to the default value of 2042.
Includes:
- Sensor driver at drivers/sensor/bflb/bflb_tsen/
- DT binding for compatible "bflb,tsen"
- TSEN nodes (disabled) in bl60x, bl61x, bl70x, bl70xl dtsi files
Tested on BL602, BL616, BL706, and BL704L hardware.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Switch all Espressif partition layouts from the deprecated
fixed-partitions binding to the new zephyr,mapped-partition
binding introduced in the Zephyr 4.4 migration. Update the
flash-controller and flash0 nodes to declare the ranges and
address/size cells required by the new binding so partition
offsets resolve correctly through the node hierarchy.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add board definition for the Sipeed M0Sense, a compact development
board based on the BL702SA0Q2I (QFN32) with USB-C, RGB LED, user
button, and castellated pads. Console is via USB CDC-ACM.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Rename BL61x GPIO and pinctrl drivers to bl61x_808 variants since
BL808 shares identical register layouts. Update compatible strings,
Kconfig, CMakeLists, and BL61x device tree accordingly. Extend the
DMA and IR receiver drivers' BL61x guards to also cover BL808.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add device tree source for Bouffalo Labs BL808 SoC with T-Head E907
core, including peripherals (UART, SPI, I2C, GPIO, PWM, WDT, timer,
RTC, DMA, ADC, sec_eng), clock tree, flash controller, and memory
regions (ITCM, OCRAM, WRAM, MM DRAM/VRAM).
Also adds the BL808 clock controller DT binding and clock ID header.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Introduce a single "bflb,bt-hci" compatible for all Bouffalo Lab
on-chip BLE controllers, replacing the per-SoC "bflb,bl70x-bt-hci"
and "bflb,bl70xl-bt-hci" strings. Update both bl70x.dtsi and
bl70xl.dtsi to use the unified compatible.
Add the bt-hci node (disabled by default) to bl70xl.dtsi for
boards that enable BLE support.
Promote the retram node (HBN RAM at 0x40010000) to a proper
zephyr,memory-region so BLE vendor blob sections (.hbn_code,
.retention_noinit) can be placed there by the linker.
Signed-off-by: William Markezana <william.markezana@gmail.com>
ESP32-C2 and ESP32-C3 implement the zifencei extension (fence.i)
but their device trees declared only "i", "m", "c", "zicsr".
Adding zifencei selects rv32im_zicsr_zifencei/ilp32, the atomic-free
multilib, fixing illegal instruction faults on picolibc paths that
touch stdio locking.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The driver provides basic RTC functionality including time read and
write, alarm configuration(alarm1 and alarm2), and daylight saving
time (DST) support.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
