Add it515xx analog to digital converter driver which supports 8 channels
ch0 ~ ch7 and 12-bit resolution.
Signed-off-by: Yunshao Chiang <Yunshao.Chiang@ite.com.tw>
The device tree entry for cva6 is currently missing a device tree node
for the mtime and mtimecmp registers in the core-local interrupt
controllers.
This causes the RISC-V machine timer driver not to be built, causing
build failures as the system clock is missing.
This commit rectifies this by adding the corresponding device tree
entry.
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
Adds support for the CVA6 family of RISC-V CPUs.
CVA6 is commonly found as a soft core CPU on FPGA designs.
Different configurations and instruction set extensions can be
configured, and different SoCs targeting various FPGA boards are
available.
This commit adds support for the 32-bit and 64-bit configurations
of CVA6, as well as three slightly different SoCs (a minimal 32-bit
configuration, a 64-bit configuration without FPU, a 64-bit
configuration with FPU).
Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
The IT8xxx2 timer driver uses timer 7 and timer 8 to implement the alarm
timer and the top timer, respectively.
Signed-off-by: Yunshao Chiang <Yunshao.Chiang@ite.com.tw>
Use vendor prefix "neorv32" for all peripherals provided by the NEORV32
RISV-V Processor project.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This patch adds an initial driver for the WCH DMA
controller. All hardware features and most interface
features are implemented.
Signed-off-by: Paul Wedeck <paulwedeck@gmail.com>
Update the NEORV32 SoC, peripheral drivers, and board to support NEORV32
v1.11.1. Notable changes include:
- Optional RISC-V ISA Kconfigs are now selected on the board level.
- Peripheral registers are now automatically reset in hardware, no need for
software initialization code.
- The NEORV32 GPIO controller now supports 32 pins, not 64. Interrupt
support will be submitted in a separate PR.
- Default board configuration has 64k RAM and is clocked at 18 MHz.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit renames the KSO16 and KSO17 for consistency with the naming
convention used for other KSO pins.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
ADC2 is no longer supported on ESP32C3 due to HW limitations.
Check silicon errata on Espressif website for more details.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
This commit replaces a bunch of ifdefs and bindings with a single
extensible binding, and makes all standard mtime system timers consistent.
Signed-off-by: Camille BAUD <mail@massdriver.space>
The CH32V003 belongs to the CH32V0 series. To improve code organization
and maintainability, all related files should be grouped together in a
dedicated subdirectory.
Signed-off-by: Jianxiong Gu <jianxiong.gu@outlook.com>
Fixes misassignment of cpuflpr_vevif label to cpuppr_vevif_tx node by
instead assigning to cpuflpr_vevif_tx node.
Signed-off-by: Daniel Mangum <georgedanielmangum@gmail.com>
The it8801 template is helpful but in the current state it does not
allow changing the device address as that is in the template itself. Fix
that by moving the template content down a level in the hierarchy, so
that it extends the mfd device itself rather than than instantiate it,
then the base instance can have any address, now the only limitation is
that only one instance is possible, but that is probably alright for
now.
Alternatives would be to use a define for the address, or even a
template per address, but this feels like a better compromise for now.
This may also use
https://github.com/zephyrproject-rtos/zephyr/pull/82825 in the future if
that ever becomes a thing.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
