Mark unused pinctrl and wuc nodes in it8xxx2 with /omit-if-no-ref/,
so that they are omitted from the final devicetree when not referenced.
After this change, test: "west build -p always -b it8xxx2_evb" shows a
reduction in devicetree size:
Before:
build/zephyr/zephyr.dts 164,449 bytes
build/zephyr/include/generated/zephyr/devicetree_generated.h
3,125,359 bytes
After:
build/zephyr/zephyr.dts 124,108 bytes
build/zephyr/include/generated/zephyr/devicetree_generated.h
1,892,313 bytes
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit prefixes pre-generated nodes with
`/omit-if-no-ref/` to keep the generated devicetree
C headers minimal.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Add device tree node for ESP32-C6 SoC ROM at 0x40000000.
This 320KB ROM contains libc and utility functions used by
the application. PMP protection is configured separately
via PMP_SOC_REGION_DEFINE in pmp_regions.c.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Set default values for BLE HCI buffer configuration that match
the ESP32 controller requirements:
- BT_BUF_ACL_RX_COUNT=24: Match controller's ACL buffer count
- BT_BUF_EVT_RX_COUNT=30: Match controller's event buffer count
Enable BT HCI node in device tree for all ESP32 SoCs that
support BLE.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Many dts/dtsi files where its dt-bindings are in-tree
do not include zephyr prefix in the #include path.
Add it to make it consistent globally.
Some dt-bindings that resides in hal can not be changed.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Adds separate memory regions for rtc ram memory areas and reworks linker
scripts to make use of their starting addresses and lengths
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
move changeable peripherals from dtsi to board, as
in litex these can change and might be on
different registers on custom out of tree
boards. So we limit riscv32-litex-vexriscv.dtsi
to just the interrupt controller and the cpu,
which don't change.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Move Xuantie supprot from arch/riscv/core/xuantie to the custom common
layer arch/riscv/custom/thead, with the following changes:
1. Rename Kconfig name
CACHE_XTHEADCMO -> RISCV_CUSTOM_CSR_THEAD_CMO
2. Split the original arch/riscv/core/xuantie/Kconfig to
a. arch/riscv/custom/thead/Kconfig: for T-Head extension
b. arch/riscv/custom/thead/Kconfig.core: for T-Head CPU series
(e.g. Xuantie E907)
3. Move cache line size defaults to SoC devicetree
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
TLSR951x also supports Andes extended CSR. Reworks the following CSR
handling to use the RISC-V custom CSR common code:
1. Use common macros for HWDSP CSR context save/restore.
2. Use common macros for PFT CSR context save/restore.
3. Use common low-level CSR initialization via __reset hook.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This is a SOC based on AE350. In addition to the core, some
modifications have been made to the peripheral functions,
including the integration of built-in USB.
Signed-off-by: Jacky Lee <jacky.lee@egistec.com>
Fix compatible name on device tree, to allow RTC timer based
counter driver to be enabled. Disable rtc_timer node for all
devices to keep standard.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
