The flash M1K driver supports read (up to 1K), write (1K), and
erase (4K) operations, which can be accessed via DLM.
Accessible flash regions include internal e-Flash or external SPI
flash via FSCE# or FSCE1#.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Reorganize and update soc folder files for SDK-independance
Reorganize and update hal_bouffalolab files for SDK-independance
Reorganize and update soc dts files for SDK-independance
Update serial and pinctrl driver files for SDK-independance
Update ai_wb2_12f, bl604e_iot_dvk, and dt_bl10_dvk
to new bl60x support
and fixup openocd config of ai_wb2_12f
Signed-off-by: Camille BAUD <mail@massdriver.space>
Add support the host I/O over eSPI peripheral channel for private
channel.
The default port number of ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM
for ITE SoC is 0x68.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Remove unused DMA clock property from device tree. Clock will
be managed by DMA driver for devices with GDMA peripheral.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Add driver for Microchip PolarFire SoC (MPFS) peripheral clock and soft
reset control.
Normally, the peripheral clocks and reset state are controlled by the
Hart Software Services (HSS) running on the Monitor processor. As an
alternative to using HSS services, applications can now enable the reset
controller in a device tree overly, for example:
&reset {
status = "okay";
};
&uart4 {
resets = <&reset MSS_RESET_ID_MMUART4>;
};
Embedded the reset controller node in system controller node.
Signed-off-by: Frank Kühndel <frank.kuehndel@embedded-brains.de>
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
The CH32V003 has a 8 channel, 10 bit onboard ADC. Add an immediate
mode driver and the appropriate pinctrl bindings. Note that the
CH32V003 GPIO pins have both a floating input and an analogue input
mode, and the pinctrl is needed to put the pin in analogue mode.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The WCH External Trigger and Interrupt controller (EXTI) supports
between 8 and 22 lines where each line can trigger an interrupt on
rising edge, falling edge, or both edges. Lines are assigned to a
group, and each group has a separate interrupt. On the CH32V003/6,
there is one group of 8 lines, while on the CH32V208 there are
multiple groups with between one and six lines per group.
In the same way as the STM32 and GD32, define an EXTI driver that
configures the peripheral and an internal interface that can configure
individual lines.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The CH32V20x and CH32V30x SoCs have 16 pins per GPIO bank, but in the
devicetree, `ngpios` was incorrectly set to 8.
Fix the devicetrees by setting the correct value.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
This enables the clock_control driver build on bl60x.
It is currently deferred init, due to being incompatible
with current SDK-based boot, to avoid later giant PR.
Signed-off-by: Camille BAUD <mail@massdriver.space>
The driver originally supported only it8xxx2 series. This updates
introduces compatibility allow it to also support it51xxx series
with minimal changes.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Timer 7 is not used in timer driver, which means that timer
driver doesn't initialize timer 7, it's just declared in dtsi.
So I remove it, timer 7 will be used as alarm timer for counter driver.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Current ESP32 clock system is mixed with RTC labeling/registers,
but it doesn't implement a real-time clock (RTC) driver.
To avoid confusion and allow adding a proper RTC driver later,
this commit renames the existing RTC interface to CLOCK and make
it as a subsystem without any peripheral attached to it.
This better reflects its actual purpose as a general clock controller.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
1. Add it51526bw SoC variant to it51xxx SoC series.
2. Create the .dtsi file with adjusted flash size for 512Kb (default = 1M).
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Commit 42fb9067e4 makes it mandatory to
now have reg-names property on the riscv,machine-timer node. This DTS
file was somehow missed as part of the refactoring.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This commit updates all relevant device tree source files using the
riscv,machine-timer binding to explicitly define `reg-names` for the MTIME
and MTIMECMP registers.
This change ensures compatibility with the updated riscv_machine_timer
driver, which now relies on `reg-names` to resolve register addresses
instead of using fixed index positions.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
ElemRV-N is based on the nitrogen SoC platform. Add the
base nitrogen device-tree and one for elemrv-n. The elemrv-n
device-tree will contain all IP cores later.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
