Add reset driver for the reset part of the ch32 rcc.
Use this new reset driven in `wch,usart` to reset the usart peripheral
before use.
Signed-off-by: Fiona Behrens <me@kloenk.dev>
Move dts parameters common to nrf7120 and nRF7120e into common file.
Add nrf7120e specific dts files.
Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
Add board, SoC, and devicetree support for ElemRV-H, an open-source
RISC-V microcontroller built on the Hydrogen platform.
The Hydrogen SoC integrates a VexiiRiscv core (RV32I_Zicsr_Zifencei)
clocked at 50 MHz with UART, GPIO, and pin multiplexer peripherals.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Move the ite,it8xxx2-pinctrl container node from the /soc node to the
root / node.
The pin-controller node is a logical container for pin configuration
states rather than a memory-mapped bus peripheral on the SoC bus. When
located inside /soc, DTC treats its children as addressable by the SoC
bus address/size cells, triggering avoid_unnecessary_addr_size
warnings/errors. Moving it to the root matches the convention used across
other SoC families in Zephyr (such as npcx and rp2040).
Assisted-by: Antigravity:gemini-1.5-pro
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Allign the devicetree structure of the wch ethernet
nodes wich the other existing nodes, that also use the
Synopsys Designware IP.
Signed-off-by: Fin Maaß <info@finmaass.de>
As per our documentation, we have to
reuse bindings from Linux, there they use
"snps,dwmac-mdio", so let's use the same one
here in zephyr.
Signed-off-by: Fin Maaß <info@finmaass.de>
As per our documentation, we have to reuse bindings from Linux, there
they use "snps,dwmac-mdio", so let's use the same one here in zephyr.
The esp32 itself is not in Linux, but the ethernet IP from Synopsys is.
Signed-off-by: Fin Maaß <info@finmaass.de>
Remove unnecessary #address-cells and #size-cells properties from the
ite,it8xxx2-pinctrl node. These properties are not needed because the
pin-controller node does not have any memory-mapped child nodes with
reg properties, and their presence triggers an
avoid_unnecessary_addr_size DTC warning.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Describe the EMAC PTP reference clock as a second clock on the
esp32p4 Ethernet node so it can be enabled and queried through
the clock control driver.
The rate is resolved from the PTP reference clock source, so
Ethernet PTP support does not need to assume a fixed frequency.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add disabled-by-default ana_cmpr nodes for the SoCs that have this
peripheral: two units on ESP32-P4 (sharing GPIO_PAD_COMP_INTR_SOURCE)
and one unit each on ESP32-C5 (GPIO_EXT_SOURCE) and ESP32-H2
(GPIO_INTR_SOURCE, shared with the GPIO peripheral's own interrupt).
Signed-off-by: Tiago Medicci <tiago.medicci@espressif.com>
This commit introduces the following changes:
- Add device tree definitions for the Qingke V3C cpu
- Add device tree definitions for the CH570 SoC
- Add bindings for UART, GPIO and pin control
Signed-off-by: Elie Carrot <elie.carrot@smile.fr>
The driver supports up to nine SMBus controllers and implements the
standard SMBus protocols, except for Block Process Call.
It also supports an optional FIFO mode that uses the controller's
dedicated 32-byte FIFOs to reduce the interval between transferred
bytes and improve clock stretching during SMBus transactions.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add the disabled can@2000aa00 controller node for the BL61x SoC, to be
enabled per-board. The node uses the bflb,bl61x-can binding and CLIC
interrupt 46.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add a SIP-level dtsi for ESP32-P4 variants combining 16 MB of
external NOR flash with 32 MB of in-package PSRAM, mirroring the
existing esp32p4_n16r8.dtsi. Used by the Waveshare
ESP32-P4-WIFI6-Dev-Kit board.
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
Extend the WCH RCC clock driver for the CH32H41X series. Add the H41X
PLL binding and SoC clock node, handle the H41X clock-enable register
names and FPRE prescaler, and implement the 480 MHz SYSCLK and
120 MHz HCLK bring-up sequence.
Select the H41X-specific path from the RCC source compatible in
devicetree. Existing CH32V00X, CH32V20X, and CH32V30X configurations
remain unaffected.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
Add the CH32H41X SoC series under the ch32v family. The CH32H417 is
an asymmetric dual-core (AMP) RISC-V part with a QingKe V3F boot
core and a QingKe V5F application core.
Model the two cores as cpuclusters with separate CPU descriptions,
runtime-idle power states, interrupt entry, vector handling, and
non-overlapping memory. Keep the external HSE frequency
board-specific.
The optional SOC_CH32H417_BOOT_V5F setting lets the V3F early-init
hook wake the V5F image at its real flash address, 0x08010000, while
allowing standalone V3F applications to disable that behavior.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
Add SIP-level dtsi files for 32 MB flash ESP32-P4 variants:
esp32p4_n32r32.dtsi for the ESP32-P4NRW32 SIP (32 MB in-package
PSRAM and 32 MB external NOR flash) and esp32p4_lpcore_n32.dtsi
for the LP core on 32 MB flash parts.
Also add a default 32 MB partition layout with the 0x2000 boot
offset, mirroring the existing 0x1000 32 MB layout.
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
Apply the default pinctrl state during PM_DEVICE_ACTION_RESUME to restore
normal SHI operation.
Apply the sleep pinctrl state during PM_DEVICE_ACTION_SUSPEND to disable
the SHI interface pins and prevent leakage.
This lets board/shim code control the pin state purely via
pm_device_runtime_get()/put().
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The MRAMC driver requires write-block-size to be a multiple of the
16-byte MRAM word size. Set write-block-size to 16 to match the
hardware constraint and the cpuapp_mram definition.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
This commit removes a redundant HSE clock frequency definition for wch.
This value is really dependent on the component placed on a board, so
two layers of default are not necessary.
Signed-off-by: Perry Naseck <pnaseck@media.mit.edu>
Adds SoC support for SHAKTI Ganga, a 64-bit
RISCV SoC from SHAKTI processor initiative at
RISE Lab, IIT Madras. Ganga is commonly ran as
soft core on FPGA boards.
This commit adds SoC family Kconfig and
the base devicetree.
Signed-off-by: Vedant Malkar <vedantitsme@gmail.com>
Add non-cacheable memory support on the esp32p4 by reserving a
power-of-two window at the top of HP SRAM and marking it
non-cacheable with a PMA NAPOT entry at boot. The window keeps its
normal cached address so it stays reachable by the DMA engine,
while CPU accesses bypass the cache, so both masters see coherent
data through one address.
The region size comes from the sramhp_nocache devicetree node and
the base is derived per silicon revision, whose SRAM and cache
layouts differ. The PMA entry is re-applied on wake from standby
because the PMA CSRs are volatile across CPU power-down sleep.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add esp32c5 and esp32p4 support to the esp32 mailbox driver. The HP and
LP cores signal each other through the PMU software interrupt, the same
mechanism used on the esp32c6, with the esp32p4 LP interrupt status bit
handled per its register layout.
The esp32p4 LP core uses a multi-vectored interrupt controller that
jumps directly to the handler, so tag the LP PMU handler with
LP_CORE_ISR_ATTR so it saves and restores registers and returns with
mret; on the single-vector esp32c5 and esp32c6 the attribute is empty.
Also shrink the esp32p4 LP ulp_ram region so it stops before the shared
ulp_shm block that holds the mailbox coordination data, matching the HP
view and preventing the loader from clobbering it.
Mark the esp32c5 and esp32p4 mailbox nodes okay to match the other socs.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Several peripheral reg sizes in rv32m1.dtsi are too small and do not
cover their full documented register maps.
Update the affected ranges to match the actual peripheral layouts:
gpio*: 0x14 -> 0x40 PDDR @ 0x14 ends at 0x18; 0x40 matches
the 0x40-aligned port slots and every
other Kinetis dtsi (nxp_kw41z, nxp_k6x,
nxp_k2x, nxp_k8x, nxp_ke1x*).
lpuart*: 0x2C -> 0x1000 WATER @ 0x2C ends at 0x30; 0x1000
matches nxp_k8x and nxp_k32l2b3.
lpi2c*: 0x170 -> 0x1000 SRDR @ 0x170 ends at 0x174; 0x1000
matches the 0x1000-spaced layout.
pcc*: 0x200 -> 0x1000 CLKCFG[130] runs to 0x208; 0x1000
matches nxp_ke1xf/nxp_ke1xz.
intmux1: 0x20 -> 0x200 Typo - intmux0 (same IP, same struct)
is 0x200.
Signed-off-by: Adrian Śliwa <asliwa@internships.antmicro.com>
Add the ESP32-P4 USB-OTG high-speed controller using the
espressif,esp32-usb-otg-hs binding and the internal UTMI PHY. The
high-speed PHY uses dedicated pins, so no pad configuration is
needed. Enable the controller on the function ev board.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add the ESP32-P4 USB-OTG full-speed controller node using the
espressif,esp32-usb-otg-fs binding, with the internal PHY D+/D- pad
numbers provided through the phy-dp-pin and phy-dm-pin properties.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Updated QEMU AIA board variants to implement the ISA extensions SMAIA
and SSAIA as defined in the AIA specification.
Signed-off-by: Omar Naffaa <onaffaa@qti.qualcomm.com>
Extend bflb_rf_init() to support WiFi mode (WL_API_MODE_ALL) with
TX power targets and country code configuration when CONFIG_BFLB_WIFI
is enabled.
Add WiFi platform glue: MAC ISR wiring, task creation, low-power
stubs, wl80211 RTOS primitives (heap, RNG, timers), and the linker
section for WiFi shared RAM.
Introduce CONFIG_BFLB_BL61X_WL_RMEM_SIZE for PHY/RF retention memory
sizing.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add the wifi0 node for the BL61x WiFi MAC peripheral at 0x24b08000
with its devicetree binding.
Introduce bl61x_em_32kb_wifi.dtsi which carves 128 KB from WRAM for
WiFi MAC shared structures (TX/RX descriptors, IPC) via the
non-cached bus-remap alias, and scales sram1 down to 32 KB.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Update the driver used for ESP32, ESP32-S2 and ESP32-S3 to the
latest version and add support for ESP32-P4.
Signed-off-by: Tiago Medicci <tiago.medicci@espressif.com>
- systick: split multi-statement lines into one per line (Zephyr style)
- ch32v103.dtsi: add missing reg property alongside ranges in flash0 node
Signed-off-by: Lucy Wong <mova845@outlook.com>
The ADTM is a superset of the GPTM and has the same core register
layout. See section 11.2.2 of the CH32V003RM for details on the
differences.
Use the same technique as the GD32 driver, i.e. use the same basic
driver with tweaks based on the features.
Add the common 3x GTPM and 1x ADTM Devicetree and pinctrl entries for
the 20x and 30x series and the extra 1x GPTM for the CH32V208 used in
linkw. I can follow up with the other chips in a separate PR.
Tested on the ch32v006evt and linkw by running
`samples/basic/blinky_pwm` and `tests/drivers/pwm/pwm_api` and
checking the output with a logic analyser.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Wire the gdma driver to the esp32p4 AXI and AHB DMA instances,
selecting the per-bus LL calls and 8-byte aligned descriptors so
both buses work through the common driver.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a controller and PHY driver for the BL808 UHS PSRAM. The PHY read/write
eye is calibrated at boot by sweeping the DQS/DQ delay taps and latency, so
any supported rate works without per-rate constants. Add the devicetree
nodes and enable on the M1S Dock.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add the UHS PLL, a dedicated PLL that feeds only the UHS PSRAM PHY. It is
outside the system clock tree and brought up on demand; the output
frequency comes from the clk_uhspll devicetree node.
Signed-off-by: William Markezana <william.markezana@gmail.com>
