Update the NEORV32 SoC, peripheral drivers, and board to support NEORV32
v1.11.1. Notable changes include:
- Optional RISC-V ISA Kconfigs are now selected on the board level.
- Peripheral registers are now automatically reset in hardware, no need for
software initialization code.
- The NEORV32 GPIO controller now supports 32 pins, not 64. Interrupt
support will be submitted in a separate PR.
- Default board configuration has 64k RAM and is clocked at 18 MHz.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit renames the KSO16 and KSO17 for consistency with the naming
convention used for other KSO pins.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
ADC2 is no longer supported on ESP32C3 due to HW limitations.
Check silicon errata on Espressif website for more details.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
This commit replaces a bunch of ifdefs and bindings with a single
extensible binding, and makes all standard mtime system timers consistent.
Signed-off-by: Camille BAUD <mail@massdriver.space>
The CH32V003 belongs to the CH32V0 series. To improve code organization
and maintainability, all related files should be grouped together in a
dedicated subdirectory.
Signed-off-by: Jianxiong Gu <jianxiong.gu@outlook.com>
Fixes misassignment of cpuflpr_vevif label to cpuppr_vevif_tx node by
instead assigning to cpuflpr_vevif_tx node.
Signed-off-by: Daniel Mangum <georgedanielmangum@gmail.com>
The it8801 template is helpful but in the current state it does not
allow changing the device address as that is in the template itself. Fix
that by moving the template content down a level in the hierarchy, so
that it extends the mfd device itself rather than than instantiate it,
then the base instance can have any address, now the only limitation is
that only one instance is possible, but that is probably alright for
now.
Alternatives would be to use a define for the address, or even a
template per address, but this feels like a better compromise for now.
This may also use
https://github.com/zephyrproject-rtos/zephyr/pull/82825 in the future if
that ever becomes a thing.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
IT8801 support GPIO alternate function switching.
Some GPIO pins can be switched as KSO or PWM function.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
In most implements, the msip base address is 0x2000000. But the address
is not fixed in all boards.
Signed-off-by: Yang Jialong <yangjialong@vcore.com>
This commit adds the clock driver for WCH CH32V003.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This commit adds the dtsi and bindings for the WCH CH32V003 which is a
32-bit general-purpose RISC-V MCU.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
* Replace copies of fixed-partitions nodes in related boards by
referencing the apropriate partition table from the available list.
* For better reference the `partitions_*.dtsi` file has boot offset,
purpose and the flash size encoded in the file name. Default flash size
is considered to be 4MB.
* Added the flash size node for the boards which are not based on the
module.
* Removed flash size registry from the esp32.*common.dtsi
Signed-off-by: Marek Matej <marek.matej@espressif.com>
These two new ICs are variants of the nRF54L15 with different memory
sizes:
- nRF54L05: 500KB RRAM, 96KB RAM
- nRF54L10: 1022KB RRAM, 192KB RAM
- nRF54L15: 1524KB RRAM, 256KB RAM
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add `hifive_unmatched//s7` (earlier selected by default, using
`hifive_unmatched`) and `hifive_unmatched//u74` targets.
Define work-area for other 4 cores in openocd.cfg
Update twister platform white/black lists, to support new targets
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Add `hifive_unleashed//e51` (earlier selected by default, using
`hifive_unleashed`) and `hifive_unleashed//u54` targets.
Define work-area for other 4 cores in openocd.cfg
Update twister platform white/black lists, to support new targets
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adjusts the sizes of the two PLIC nodes AE350 defines:
* `plic0` size is changed from `0x04000000` to `0x02000000`
* `plic_sw` size is changed from `0x04000000` to `0x00400000`
Without these change, `plic0` address space would overlap with `plic_sw`,
and with other memory-mapped peripherals.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Renamed andestech,plic-sw to andestech,mbox-plic-sw because the mbox node
is based on the PLIC interrupt controller node instead using the plic
hardware directly.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The plic-sw is the same hardware as the plic interrupt contoller and should
be used with intc_plic driver instead of separate mbox driver.
Renamed plic-sw node from "mbox: mbox-controller@e6400000" to
"plic_sw: interrupt-controller@e6400000".
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The production version of the nRF54L15 SoC is now available, so remove
the initial Engineering A (EngA) preview version.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add board support for eval board ganymed_bob, which
is a break-out-board for both soc variants.
Variants of the soc are GBM and GEN1.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
I2S driver was merged after interrupt .dtsi was changed,
causing CI to fail. This updates it accordingly.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
