The driver provides basic RTC functionality including time read and
write, alarm configuration(alarm1 and alarm2), and daylight saving
time (DST) support.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Region size defined for lp_uart and lp_gpio on c5/c6 does not match TRM.
Reduce to 1kB per TRM.
Signed-off-by: Jacob Schloss <jacob.schloss@suburbanmarine.io>
Enable the GPIO peripheral for the nRF54H20 FLPR core.
Add the corresponding test overlays so that the
tests run correctly under Twister for the FLPR core.
Signed-off-by: Paweł Pelikan <pawel.pelikan@nordicsemi.no>
The ulp_shm DTS node at 0x3bf0 overlapped with the last
16 bytes of the ulp_ram region (0x0..0x3c00) on both
ESP32-C5 and ESP32-C6.
Move ulp_shm to 0x3c00, right after ulp_ram, and shift
lp_rtc from 0x3c00 to 0x3c10 (shrinking it by 16 bytes
from 0xf8 to 0xe8) to make room. All other regions
(retainedmem, ipc_shm, mbox0) keep their addresses.
Update LP core linker scripts to stop subtracting
shared mem size from the ram segment length, since
ulp_shm is now outside the coprocessor reservation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add devicetree binding for the Bouffalo Lab BL70x USB 1.1 Full-Speed
device controller and define the USB peripheral node in bl70x.dtsi.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Set cpu-buffer-stall property on the BL70x USB peripheral node to
ensure proper buffer alignment for DMA transfers.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add devicetree source files, clock definitions, interrupt mapping,
GPIO signal map, and pin control bindings for ESP32-C5.
Also add 8 MB flash partition layout with 0x2000 offset and extend
the espressif,riscv CPU binding to accept 48 MHz XTAL frequency.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add an HCI driver for the BL702 on-chip BLE controller. The controller
is a precompiled binary blob communicating via vendor on-chip HCI
functions (bt_onchiphci_send/bt_onchiphci_interface_init).
The driver:
- Translates between Zephyr HCI net_buf and the vendor's internal
packet structures for both TX (commands, ACL data) and RX (events,
ACL data)
- Uses a dedicated RX thread with FIFO+semaphore to dequeue messages
from the controller callback (which may run in ISR context)
- Reads the BLE MAC address from eFuse during initialization
- Supports multiple controller binary variants via Kconfig choice
(peripheral-only, multi-role, observer, etc.)
- Provides proper open/close lifecycle with RX queue draining
Also adds the DT binding (bflb,bl70x-bt-hci) and a bt-hci node in
the BL70X SoC dtsi (disabled by default).
Signed-off-by: William Markezana <william.markezana@gmail.com>
# Conflicts:
# drivers/bluetooth/hci/CMakeLists.txt
Removes resource reservation for cpuflpr from the cpuapp build and
only applies it when either of the flpr snippets are used
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
This adds initial support for the CH32V ethernet peripheral.
The driver supports both internal and external PHY configurations.
Signed-off-by: James Bennion-Pedley <james@bojit.org>
Add device tree nodes for the Bouffalo Lab SEC Engine sub-blocks
(SHA, AES, GMAC) across all three SoC families:
- bl60x/bl70x: individual IRQs per sub-block (SHA=30, AES=29,
GMAC=25), peripherals at 0x40004xxx
- bl61x: shared IRQ 26 for all crypto sub-blocks
(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn), peripherals at
0x20004xxx
Add corresponding DT binding YAML files for each compatible.
Enable SEC_ENG AES and SHA nodes on ai_m62_12f_kit,
ai_wb2_12f_kit, and dt_xt_zb1_devkit boards.
Signed-off-by: William Markezana <william.markezana@gmail.com>
# Conflicts:
# dts/riscv/bflb/bl60x.dtsi
# dts/riscv/bflb/bl61x.dtsi
# dts/riscv/bflb/bl70x.dtsi
Add ranges, #address-cells and #size-cells to cpuflpr_mram to
match the cpuapp_mram pattern. Without these the fixed-partitions
child node causes dtc warnings about mismatched address-cells and
default addr/size reliance.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
Add an entropy driver for Bouffalo Lab BL70X that reads
random data from the SEC TRNG block and wires it into
Zephyr's entropy API.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Adjust PM residency times to more realistic values. Add power
states to ESP32-C2. Mark soft-off state as disabled, as it must
be called explicitly by application.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
- Fix lp_gpio Kconfig dependency to use proper
DT_HAS_ESPRESSIF_ESP32_LPGPIO_ENABLED symbol instead of
SOC_ESP32C6_LPCORE, and separate GPIO_ESP32 from LPGPIO_ESP32
- fix lp_gpio compatible string to espressif,esp32-lpgpio to
match the corrected Kconfig dependency
- enable global LP core interrupts at startup via
ulp_lp_core_intr_enable() in lp_core_startup(); the LP core
has no interrupt allocator so this must be done once for any
peripheral using the single interrupt vector
- enable lp_gpio in gpio_wakeup sample overlay
- fix ESP_CONSOLE_UART_NUM default for LP HP UART console
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Reorganize ESP32-C6 LP SRAM into dedicated memory regions:
- ulp_shm: ULP shared memory for LP core communication
- ipc_shm: IPC shared memory for mbox driver
- lp_rtc: RTC data section for deep sleep persistence
- retainedmem: retained memory region with zephyr,retained-ram
Reduce main LP SRAM from 16K to 15K to accommodate the new
dedicated regions in upper LP SRAM. Update mbox overlay
references from shmlp to ipc_shm nodelabel.
Remove deep_sleep and retained_mem board overlays that are no
longer needed with the updated base DTS.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The cva6.dtsi contains bad reg values for eth and gpio peripherals.
The form reg=<0x0 base 0x0 size> has been replaced with expected
reg=<base size>.
Signed-off-by: Egon Carusi <egon.carusi@swhard.it>
Add a watchdog timer driver for all Bouffalo Lab SoC families.
Tested on Sipeed M0Sense (BL702) with tests/drivers/watchdog/wdt_basic_api.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Removes resource reservation for cpuflpr from the cpuapp build and
only applies it when either of the flpr snippets are used
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Apply chnages from dts-linter 0.3.9.
Improve compliance with DTS Coding Style which says that:
4) Hex values in properties, e.g. “reg”, shall use lowercase hex.
The address part can be padded with leading zeros.
Signed-off-by: Kyle Bonnici <kylebonnici@hotmail.com>
In WCH chips entering idle via `wfi` will break ongoing DMA
transactions. This adds PM state to prevent `wfi` idle in specific drivers.
Signed-off-by: James Bennion-Pedley <james@bojit.org>
