soc: nordic: Remove the nRF54L15 EngA
The production version of the nRF54L15 SoC is now available, so remove the initial Engineering A (EngA) preview version. Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
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cb47c62259
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51c1e45301
17 changed files with 5 additions and 3476 deletions
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@ -10,13 +10,8 @@
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#include <haly/nrfy_vpr.h>
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#if defined(CONFIG_SOC_NRF54L15_ENGA_CPUAPP)
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#define EVENTS_IDX_MIN 11U
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#define EVENTS_IDX_MAX 17U
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#else
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#define EVENTS_IDX_MIN NRF_VPR_EVENTS_TRIGGERED_MIN
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#define EVENTS_IDX_MAX NRF_VPR_EVENTS_TRIGGERED_MAX
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#endif
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/* callbacks */
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struct mbox_vevif_event_rx_cbs {
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@ -12,11 +12,7 @@
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#include <hal/nrf_vpr_csr.h>
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#include <hal/nrf_vpr_csr_vevif.h>
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#if defined(CONFIG_SOC_NRF54L15_ENGA_CPUFLPR)
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#define EVENTS_IDX_MAX 17U
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#else
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#define EVENTS_IDX_MAX NRF_VPR_EVENTS_TRIGGERED_MAX
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#endif
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#define VEVIF_EVENTS_NUM DT_INST_PROP(0, nordic_events)
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#define VEVIF_EVENTS_MASK DT_INST_PROP(0, nordic_events_mask)
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@ -12,13 +12,8 @@
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#include <hal/nrf_vpr_csr.h>
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#include <hal/nrf_vpr_csr_vevif.h>
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#if defined(CONFIG_SOC_NRF54L15_ENGA_CPUFLPR)
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#define TASKS_IDX_MIN 11U
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#define TASKS_IDX_MAX 17U
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#else
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#define TASKS_IDX_MIN NRF_VPR_TASKS_TRIGGER_MIN
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#define TASKS_IDX_MAX NRF_VPR_TASKS_TRIGGER_MAX
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#endif
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#define VEVIF_TASKS_NUM DT_INST_PROP(0, nordic_tasks)
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#define VEVIF_TASKS_MASK DT_INST_PROP(0, nordic_tasks_mask)
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@ -10,11 +10,7 @@
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#include <haly/nrfy_vpr.h>
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#if defined(CONFIG_SOC_NRF54L15_ENGA_CPUAPP)
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#define TASKS_IDX_MAX 17U
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#else
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#define TASKS_IDX_MAX NRF_VPR_TASKS_TRIGGER_MAX
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#endif
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struct mbox_vevif_task_tx_conf {
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NRF_VPR_Type *vpr;
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@ -14,8 +14,7 @@
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#include <zephyr/toolchain.h>
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#include <hal/nrf_vpr.h>
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#if (defined(CONFIG_SOC_NRF54L15_ENGA_CPUAPP) || defined(CONFIG_SOC_NRF54L15_CPUAPP)) && \
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!defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
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#if defined(CONFIG_SOC_NRF54L15_CPUAPP) && !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
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#include <hal/nrf_spu.h>
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#endif
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@ -42,8 +41,7 @@ static int nordic_vpr_launcher_init(const struct device *dev)
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}
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#endif
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#if (defined(CONFIG_SOC_NRF54L15_ENGA_CPUAPP) || defined(CONFIG_SOC_NRF54L15_CPUAPP)) && \
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!defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
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#if defined(CONFIG_SOC_NRF54L15_CPUAPP) && !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
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nrf_spu_periph_perm_secattr_set(NRF_SPU00, nrf_address_slave_get((uint32_t)config->vpr),
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true);
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#endif
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@ -1,18 +0,0 @@
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/nordic/nrf54l15_cpuapp.dtsi>
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/delete-node/ &pdm20;
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/delete-node/ &pdm21;
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&cpuapp_vevif_rx {
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nordic,events-mask = <0x00008000>;
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};
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&cpuapp_vevif_tx {
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nordic,tasks-mask = <0x0003f800>;
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};
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@ -1,25 +0,0 @@
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <riscv/nordic/nrf54l15_cpuflpr.dtsi>
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/delete-node/ &pdm20;
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/delete-node/ &pdm21;
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&cpuflpr_vevif_rx {
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nordic,tasks-mask = <0x0003f800>;
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interrupts = <11 NRF_DEFAULT_IRQ_PRIORITY>,
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<12 NRF_DEFAULT_IRQ_PRIORITY>,
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<13 NRF_DEFAULT_IRQ_PRIORITY>,
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<14 NRF_DEFAULT_IRQ_PRIORITY>,
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<15 NRF_DEFAULT_IRQ_PRIORITY>,
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<16 NRF_DEFAULT_IRQ_PRIORITY>,
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<17 NRF_DEFAULT_IRQ_PRIORITY>;
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};
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&cpuflpr_vevif_tx {
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nordic,events-mask = <0x00008000>;
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};
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@ -52,9 +52,6 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_ENGB_CPUPPR NRF54H20_ENGB_X
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NRF_PPR)
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zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_ENGB_CPUFLPR NRF54H20_ENGB_XXAA
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NRF_FLPR)
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zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_ENGA NRF54L15_ENGA_XXAA)
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zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_ENGA_CPUAPP NRF_APPLICATION)
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zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_ENGA_CPUFLPR NRF_FLPR)
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zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15 NRF54L15_XXAA)
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zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_CPUAPP NRF_APPLICATION)
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zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_CPUFLPR NRF_FLPR)
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@ -179,7 +176,7 @@ if(DEFINED uicr_path)
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endif()
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endif()
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if(CONFIG_SOC_NRF54L15_ENGA_CPUAPP OR CONFIG_SOC_NRF54L15_CPUAPP OR CONFIG_SOC_NRF54L20_ENGA_CPUAPP)
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if(CONFIG_SOC_NRF54L15_CPUAPP OR CONFIG_SOC_NRF54L20_ENGA_CPUAPP)
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dt_prop(clock_frequency PATH "/cpus/cpu@0" PROPERTY "clock-frequency")
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math(EXPR clock_frequency_mhz "${clock_frequency} / 1000000")
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zephyr_compile_definitions("NRF_CONFIG_CPU_FREQ_MHZ=${clock_frequency_mhz}")
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@ -233,8 +230,6 @@ mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGB_CPUAPP nrf54h20_engb_application.svd)
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mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGB_CPUPPR nrf54h20_engb_ppr.svd)
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mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGB_CPUFLPR nrf54h20_engb_flpr.svd)
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mdk_svd_ifdef(CONFIG_SOC_NRF54H20_ENGB_CPURAD nrf54h20_engb_radiocore.svd)
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mdk_svd_ifdef(CONFIG_SOC_NRF54L15_ENGA_CPUAPP nrf54l15_enga_application.svd)
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mdk_svd_ifdef(CONFIG_SOC_NRF54L15_ENGA_CPUFLPR nrf54l15_enga_flpr.svd)
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mdk_svd_ifdef(CONFIG_SOC_NRF54L15_CPUAPP nrf54l15_application.svd)
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mdk_svd_ifdef(CONFIG_SOC_NRF54L15_CPUFLPR nrf54l15_flpr.svd)
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mdk_svd_ifdef(CONFIG_SOC_NRF54L20_ENGA_CPUAPP nrf54l20_enga_application.svd)
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@ -1056,10 +1056,6 @@
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#include <nrfx_config_nrf54h20_ppr.h>
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#elif (defined(NRF54H20_XXAA) || defined(NRF54H20_ENGB_XXAA)) && defined(NRF_FLPR)
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#include <nrfx_config_nrf54h20_flpr.h>
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#elif defined(NRF54L15_ENGA_XXAA) && defined(NRF_APPLICATION)
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#include <nrfx_config_nrf54l15_enga_application.h>
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#elif defined(NRF54L15_ENGA_XXAA) && defined(NRF_FLPR)
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#include <nrfx_config_nrf54l15_enga_flpr.h>
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#elif defined(NRF54L15_XXAA) && defined(NRF_APPLICATION)
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#include <nrfx_config_nrf54l15_application.h>
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#elif defined(NRF54L15_XXAA) && defined(NRF_FLPR)
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File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
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@ -4,7 +4,7 @@
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config VPR_LAUNCHER
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bool "VPR launcher"
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default y
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depends on (SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR || SOC_NRF54L15_ENGA_CPUFLPR || SOC_NRF54L15_CPUFLPR || SOC_NRF9280_CPUPPR)
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depends on (SOC_NRF54H20_CPUPPR || SOC_NRF54H20_CPUFLPR || SOC_NRF54L15_CPUFLPR || SOC_NRF9280_CPUPPR)
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help
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Include VPR launcher in build.
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VPR launcher is a minimal sample built for an ARM core that starts given VPR core.
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@ -9,17 +9,6 @@ config SOC_SERIES_NRF54LX
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select HAS_NORDIC_DRIVERS
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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config SOC_NRF54L15_ENGA_CPUAPP
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select ARM
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select ARMV8_M_DSP
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_MPU
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select CPU_HAS_ICACHE
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select CPU_HAS_ARM_SAU
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select CPU_HAS_FPU
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select HAS_HW_NRF_RADIO_IEEE802154
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select HAS_POWEROFF
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config SOC_NRF54L15_CPUAPP
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select ARM
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select ARMV8_M_DSP
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select HAS_HW_NRF_RADIO_IEEE802154
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select HAS_POWEROFF
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config SOC_NRF54L15_ENGA_CPUFLPR
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depends on RISCV_CORE_NORDIC_VPR
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config SOC_NRF54L15_CPUFLPR
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depends on RISCV_CORE_NORDIC_VPR
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@ -1,14 +0,0 @@
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# Nordic Semiconductor nRF54L15 MCU
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NRF54L15_ENGA_CPUAPP
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config NUM_IRQS
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default 271
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config IEEE802154_NRF5
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default IEEE802154
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endif # SOC_NRF54L15_ENGA_CPUAPP
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@ -1,18 +0,0 @@
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# Nordic Semiconductor nRF54L15 MCU
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NRF54L15_ENGA_CPUFLPR
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config RISCV_HAS_CPU_IDLE
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bool
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config NUM_IRQS
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int
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default 287
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# As FLPR has limited memory most of tests does not fit with asserts enabled.
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config ASSERT
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default n
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endif # SOC_NRF54L15_ENGA_CPUFLPR
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@ -9,24 +9,6 @@ config SOC_NRF54L15
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help
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NRF54L15
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config SOC_NRF54L15_ENGA
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bool
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select SOC_NRF54L15
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help
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NRF54L15 ENGA
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config SOC_NRF54L15_ENGA_CPUAPP
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bool
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select SOC_NRF54L15_ENGA
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help
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NRF54L15 ENGA CPUAPP
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config SOC_NRF54L15_ENGA_CPUFLPR
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bool
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select SOC_NRF54L15_ENGA
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help
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NRF54L15 ENGA CPUFLPR
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config SOC_NRF54L15_CPUAPP
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bool
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select SOC_NRF54L15
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@ -56,7 +56,7 @@
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*/
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#define IRQ0_PRIO IRQ_DEFAULT_PRIORITY
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#define IRQ1_PRIO 0x0
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#elif defined(CONFIG_SOC_NRF54L15_ENGA_CPUFLPR) || defined(CONFIG_SOC_NRF54L15_CPUFLPR)
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#elif defined(CONFIG_SOC_NRF54L15_CPUFLPR)
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#define IRQ0_LINE 16
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#define IRQ1_LINE 17
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