Correct compilation error due to usage of DCMIPP_PIPE1 / DCMIPP_PIPE2
on platform which do not have pixel pipes by putting those caps
under #if defined(STM32_DCMIPP_HAS_PIXEL_PIPES)
Put also DCMIPP_VIDEO_FORMAT_CAP macro inside since this is only used
for AUX / MAIN pipes.
Fixes: 126aaf6b72 ("video: dcmipp: expose dcmipp caps for all 3 pipes.")
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
In 200b886d3c a deprecated kconfig
option was brought back into the driver.
Let's fix it.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The rts5912's port 80 has a FIFO. In the ISR (Interrupt Service Routine),
extract the FIFO data until the FIFO is empty, otherwise port 80 data will
be lost.
Signed-off-by: jhan bo chao <jhan_bo_chao@realtek.com>
The previous implementation had a logical error where the prescaler
could never be bypassed due to incorrect use of BIT() macro:
This patch fixes the issue by:
1. Remove BIT() wrapper from LPTMR_PRESCALER macro to use raw
devicetree property value
2. Update bypass logic to check for zero value explicitly
3. Map DTS values to hardware register values correctly:
- prescale_glitch_filter = 0 -> bypass prescaler
- prescale_glitch_filter = n -> divide by 2^n,
using register value (n-1)
The devicetree semantic is now:
- prescale_glitch_filter = <0>: No prescaling (bypass)
- prescale_glitch_filter = <1>: Divide by 2
- prescale_glitch_filter = <2>: Divide by 4
- prescale_glitch_filter = <3>: Divide by 8
- And so on...
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
i2c_map_dt_bitrate uses LOG_ERR, however, one must define (or declare) a
log module where to sink the logs. Since this sits on a header file,
it creates a hidden include order dependency: you must include
i2c-priv.h after registering or declaring a log module on your driver.
Even worse, you are force to use logging in your drivers even if you do
not want to!
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Dual data rate isn't always supported so this
config enables/disables the relevant code in
the driver.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
There is a scenario where a Bus fault occurs as the
power management isn't initialised yet and the core
is attempted to be turned off via the ssienr register.
This commit edits this so the core register is written
to after the initialisation of the power management.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
For systems where the CPU / NVIC bus are considerably
faster than the peripheral bus used for I2C, there is
a risk that the isr handler returns before I2C controller
had time to clear its interrupt status flags
This would cause immediate re-entry to isr handler
which begins read from ISR register.
During time it take to re-enter and read from ISR register,
flags had time to be cleared
The isr handler expects that a flag is set, and in this case
when its not, an assert is triggered
The solution here is to make a dummy read from the ISR register before
returning from isr handler, this forces CPU to wait as long as needed
to ensure all writes to the I2C peripheral are completed
Fixes issue #97904
Signed-off-by: Erik Andersson <erian747@gmail.com>
Since the driver allows transfer lengths up to `UINT16_MAX + 1` bytes,
and additionally the `dummy_bytes` field includes bytes sent to provide
wait cycles on the bus, the type of this field must be `uint32_t`,
otherwise it can be overflowed for RX transfers close to the maximum.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The merge buffer was previously declared as a static variable, causing it
to be shared across all I2C instances and risking data corruption when
used concurrently. Move the buffer into the driver data to make it
instance-specific and avoid race conditions.
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Add option CONFIG_ARM_SCMI_CHAN_SEM_TIMEOUT_USEC
for users to change default timeout value.
Different platform has different delay time when
scmi agent get scmi response from scmi platform.
Signed-off-by: Biwen Li <biwen.li@nxp.com>
STM32F7xx series shares several DMA configurations with
the other platforms. These changes aim to enable platform
specific DMA configuration and align them to other platforms.
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
1.Add "mux-1-dc-0-div" and "mux-2-dc-0-div" property
in mc_cgm device tree for STM clock divider setting
and set these properties in frdm_mcxe31b.dts
2.Enable STM peripheral clock in mc_cgm_clock_control_on
function
3.Support to get STM frequency from mc_cgm_get_subsys_rate
function
4.Configure STM clock in mc_cgm_init function
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
If the framebuffer size is same as the full screen, full refresh
is applied. Otherwise, partial refresh is applied.
Signed-off-by: Winteri Wang <dongjie.wang@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
Added waveshare dsi panel driver. It is on I2C bus.
Signed-off-by: Winteri Wang <dongjie.wang@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
Added mcux_lcdifv3 driver and enabled runtime mmio configuration.
Signed-off-by: Winteri Wang <dongjie.wang@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
Setup most clocks with common_clock_set_freq().
PLL and mux are preset.
Signed-off-by: Winteri Wang <dongjie.wang@nxp.com>
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
The LPTIM timer driver previously had hardcoded assumptions about
using LPTIM1 or LPTIM3, which prevented it from working with other
LPTIM instances like LPTIM2, LPTIM4, LPTIM5, and LPTIM6.
This change makes the driver work with any LPTIM instance by:
1. Adding lptim_enable_autonomous_mode() function that dynamically
detects which LPTIM instance is in use and enables autonomous
mode for instances that support it (LPTIM1, LPTIM3, LPTIM4).
LPTIM2, LPTIM5, LPTIM6 do not support autonomous mode.
2. Adding lptim_freeze_during_debug() function that handles debug
freeze configuration for all LPTIM instances across different
APB buses:
- LPTIM1: APB1_GRP1, APB3_GRP1, or APB7_GRP1
- LPTIM2: APB1_GRP1, APB1_GRP2, APB3_GRP1, or APB4_GRP1
- LPTIM3: APB1_GRP2, APB3_GRP1, or APB4_GRP1
- LPTIM4: APB3_GRP1 or APB4_GRP1
- LPTIM5: APB3_GRP1
- LPTIM6: APB3_GRP1
Both functions use DT_REG_ADDR() to compare the base address of the
configured LPTIM instance at compile time, ensuring zero runtime
overhead.
Tested on STM32U5A5 with all four LPTIM instances (LPTIM1-4).
Signed-off-by: Kamil Krzyżanowski <kamnxt@kamnxt.com>
The driver internally uses semaphores which are only available if
CONFIG_MULTITHREADING is enabled in the build.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Enable Link-Up and Link-Down interrupts. On the interrupt handling
the monitor work is scheduled to update the link status and calling
corresponding callback routine.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add support for KSZ9131 (Gigabit Ethernet Transceiver with RGMII Support).
As first starter, 100MBit/s mode is tested.
https://www.microchip.com/en-us/product/ksz9131
Signed-off-by: Tony Han <tony.han@microchip.com>
Some variants of the PCA953x family support pull-up / pull-down
resistors through registers 0x43 and 0x44 (mostly the TCAL9538 variant).
We already support input latching and interrupt masking (which is also
only present on a few variants), so let's also add support for pull-up
and pull-down resistors.
The feature can be enabled with the has-pud property in the device tree.
Signed-off-by: Marco Widmer <marco.widmer@bytesatwork.ch>
Add initial support for the AD4170-4, AD4190-4, and AD4195-4 24-bit
ADCs, including reference selection, programmable gain amplifier, ADC
conversion modes, configurable analog inputs, filter settings, and both
bipolar and unipolar operation. Supports internal and external buffered
references, and operation from a 4.75-5.25V analog supply and a
1.7-5.25V digital supply.
Signed-off-by: Kim Seer Paller <kimseer.paller@analog.com>
The Xilinx Zynq 7000 I2C controller has the following bugs:
- completion indication is not given to the driver at the end of
a read/receive transfer with HOLD bit set.
- Invalid read transaction are generated on the bus when HW timeout
condition occurs with HOLD bit set.
- If the delay between address register write and
control register write in cdns_i2c_mrecv function is more, the xfer size
register rolls over and controller is stuck.
As a result of the above, this patch disallows message transfers with
a repeated start condition following a read operation. Also disables
interrupts between the address register write and control register write
during message reception, to prevent transfer size register rollover.
Signed-off-by: Simon Maurer <mail@maurer.systems>
Add rough estimate of a worth case H264 output size.
The video_estimate_fmt_size would need more information
such as quality, profile in order to give a better
estimate for each formats so for the time being just
stick to 16bpp based size, same as for JPEG.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Addition of a helper function which takes care of dequeue
from a source video device and queue into a sink video device.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Section 4.3.7.3.6 of the I3C v1.2 specification states that a value of
0 for the max ibi size indicates an unlimited payload size. Set it to
the max it can be configured for.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Now that the ADC prescaler are set within the driver using the clock
system, remove the specific setting of the prescaler from the clock driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Some series like F1, F3, N6 and U3 use an ADC prescaler defined in the RCC.
Instead of adding specific properties in the RCC driver, use the secondary
clock system to configure the prescaler.
The ADC driver now configures the clocks depending on their presence and
their name. Three clocks can be defined:
- the register clock (mandatory for all series)
- the kernel clock (depends on series)
- the prescaler value (depends on series)
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
