Add a read-only Zephyr OTP driver for the NXP OTPC eFuse controller
found on MCX N SoCs. Only otp_read is implemented; fuse programming is
not supported. The OTP API is byte addressed while the controller reads
32-bit words; the driver handles unaligned offsets and lengths
internally.
Read verified on real hardware on frdm_mcxn236, frdm_mcxn947, mcxn947 evk,
and mcxn547 evk
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Fix R2 (CID/CSD) response ordering for the Ambiq SDHC driver.
The Ambiq HAL packs 136-bit R2 responses as a big-endian 128-bit
value with bits 127:96 in ui32Resp[0]. Zephyr's SD stack expects
cmd->response[3] to hold the highest 32 bits, matching the SDHCI
register layout used by other SDHC drivers. The existing memcpy
therefore placed the response words in reverse order, causing
sdmmc_decode_csd() to read sector_count and block_size as zero.
Replace the memcpy with a conditional copy that reverses the word
order for R2 responses and clears the unused response words for
all other response types.
Fixes#111443
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
The native_sim counter driver did not implement the counter capture API,
so the capture path could not be exercised on native_sim / in CI. There
was also no software way to inject a capture edge, unlike gpio_emul which
provides gpio_emul_input_set() for emulating GPIO events.
Implement the capture API in the native_sim counter driver and add a
test-only backend, analogous to gpio_emul:
- counter_capture_emul_input_set()/_get() (+ _dt variants) in the new
include/zephyr/drivers/counter/counter_capture_emul.h drive/read an
emulated capture input level. On a configured, enabled and matching
edge the capture callback is invoked synchronously with the current
counter value, honoring single-shot vs continuous mode.
- Supported edges are declared in devicetree via rising-edge/falling-edge
boolean properties and enforced in capture_configure(), mirroring
GPIO_EMUL_INT_CAPS.
The counter_capture test is reworked so the edge trigger is provided by a
small "trigger source" interface (trigger_src.h) with two CMake-selected
backends: gpio_src.c (GPIO loopback on real hardware) and
counter_capture_emul_src.c (emulated input on native_sim). The test body,
edge/single-shot/continuous coverage and assertions are unchanged. A
native_sim overlay and integration platform are added so the suite runs
on native_sim.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Remove `select FLASH_PAGE_LAYOUT` from any flash drivers doing so, as
this is an option to enable an API into the flash driver, not something
the flash driver itself needs.
Signed-off-by: Jordan Yates <jordan@embeint.com>
The `thread` field is not initialized, if it's being animated via
k_work_queue_run instead of k_work_queue_start.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
- The MRCC reset registers use different instance and field
names across MCX families.
Add a set of abstraction macros that select the correct
names based on the SoC family,
allowing the driver to build for the MCXL family in addition to
the existing MCX SoCs.
- Enables the RESET driver by default on the MCXL family when an
nxp,mrcc-reset node is enabled in devicetree.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Add optional clock control to the NXP LPC CRC driver so the CRC
peripheral clock is enabled during initialization when a clocks
property is present in devicetree.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Handle PHY link-down callbacks by clearing the network carrier and
returning before changing MAC/HAL state. Keep the HAL stop/config/start
sequence for link-up events where speed or duplex may have changed.
Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
Add STM32WBAx suspend-to-RAM support and hook the SoC-specific
implementation into the build when CONFIG_PM_S2RAM is enabled.
Select the custom S2RAM marking capability and add the STM32WBAx S2RAM
support source file.
Update the suspend-to-RAM path to clear the hardware standby flag as early
as possible after resume. Use standby_entered as a software indicator to
track whether standby was effectively entered and cleared, so resume
handling only restores radio state when needed.
Signed-off-by: Romain Jayles <romain.jayles@st.com>
Even though overflow is detected and data is not processed until data
stream is synchronized, it is still possible that data stream is
corrupted. If system is overloaded (multiple cores writing in parallel
to the STM), it is possible that some data will be lost and it goes
unnoticed. It can be detected by decoding unexpected STP opcode
(e.g. DATA64) or if logging message is invalid.
Add defensive measures which attempts to catch such discrepancies and
drop the message and trigger re-synchronization:
- drop message if unexpected log level is used
- drop message if hexdump data flag is not aligned with a message
length
- trigger re-synchronization if unexpected STP opcode is found
- trigger re-synchronization if STP demultiplexer returns error
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Improve handling of the ETR buffer overflow. If there is a significant
number of data generated, it is possible that the ETR buffer is
multiple time overwritten. Previously, that case was not detected and
there were crashes due to corrupted data after re-synchronization.
Now, on every TBM FULL event write index is incremented. This allows
to track relation between write and read index and proper
re-synchronization.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
There is no need to call any handler when STP decoder is back in
sync. Removing redundant code. Additionally, do not try to
process the frame if synchronization loss was just detected.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Extend callback to return a bool which indicates if decoded data is
valid. It may be valid from STP protocol perspective but decoded data
may be unexpected which indicates that data stream is corrupted. If
callback indicates invalid data decoder changes state to out of sync
and starts searching for ASYNC.
Adapted test and debug_nrf_etr module which is using the decoder with
stream from the ETR buffer.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Clear EEF before setting EERD, so if the EEF clear fails we don't need
to also clear EERD, just need to release the semaphore.
Clearing EEF is safe.
mfd_rv3032_enter_eerd can no longer be called more than once in a row
since it takes a lock, so don't read the status of EERD, just set it.
Signed-off-by: Jacob Schloss <jacob.schloss@suburbanmarine.io>
Refactor RV3032 initialization by configuring Vbackup config in MFD.
Assign PMU/BSM bit at init.
Move trickle-resistor-ohms / trickle-charger-mode to MFD dts node.
Add semaphore lock to mfd_rv3032_update_status since it is a RMW.
Poll EEBUSY at startup to allow for fast start when it is not a POR.
Check EEF flag after EEPROM write.
Adjust I2C poll times for all-byte update and single byte update.
Add function to write single eeprom reg to allow faster poll time.
Use single byte eeprom update for PMU and clock out to skip writing
eeprom when current settings are correct.
Add a k_sem around eeprom operations to protect a future case where
several MFD children are accessing eeprom at same time.
Signed-off-by: Jacob Schloss <jacob.schloss@suburbanmarine.io>
Create two Kconfig options which are used to gate compilation of the
PHY interface drivers, previously done using logic in CMake listfiles.
The first option uses the "HAS_xxx" style and is "selected" on series with
a quirk requiring turning off the ULPI clock when using the embedded FS PHY
whereas the other follows the regular driver style, but has a series gate
to prevent compilation on wrong targets (which could occur since the
compatible it checks for is vendor-agnostic).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The NXP ECSPI represents clock polarity with two separate fields:
channelConfig.polarity (SCLK_POL), the active polarity, and
channelConfig.clockInactiveState (SCLK_CTL), the level SCLK idles at
between bursts. spi_mcux_configure() set polarity from the CPOL bit but
left clockInactiveState at the kECSPI_ClockInactiveStateLow default
applied by ECSPI_MasterGetDefaultConfig().
As a result, transfers to CPOL=1 devices (SPI modes 2 and 3) ran with an
inconsistent clock: the active polarity was inverted as requested while
the idle SCLK level stayed low. Drive clockInactiveState from the same
CPOL bit so the idle level matches the configured mode.
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
- Back to back writes to counter/calendar registers such as SEC, MIN,
HOUR, DAY, MON, YEAR need to be avoided since writes to calendar
registers take 2 to 3 RTCCLK cycles to take effect.
- The implementation here is taken from TI mspm0 sdk driverlib [0]
[0]: e66677c8c8/mspm0/source/ti/driverlib/dl_rtc_common.c (L38)
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Move the configure/de-configure pair from rram_write() up to nrf_write(),
where SYNC_LOCK guarantees exclusive access for the duration of the
whole API call. The hardware write mode is then programmed exactly
once per flash_write()/flash_erase() in the standalone (non-radio-sync)
path, regardless of how many chunks the throttling loop produces.
Behaviour for non-secure (TF-M) builds is unchanged: RRAMC config is
still programmed by TF-M at boot and never touched here.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
When CONFIG_SOC_FLASH_NRF_THROTTLING is enabled, the chunking loop in
rram_write() unconditionally advances the source pointer by chunk_len
at the end of every iteration. This turns the originally-NULL pointer
into chunk_len, then 2*chunk_len, ... by the start of subsequent
iterations.
The bug only triggers when:
- CONFIG_SOC_FLASH_NRF_THROTTLING=y
- the erase length is greater than
CONFIG_NRF_RRAM_THROTTLING_DATA_BLOCK * 16 (default 256 B)
Guard the data pointer advance with an explicit data != NULL check so
the erase emulation path stays on the memset() branch for every
chunk.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
When CONFIG_SOC_FLASH_NRF_THROTTLING is enabled, the inner chunking
loop in rram_write() decrements `len` to 0 and advances `addr` past
the end of the user buffer. The commit_changes() call that follows
then always sees `len == 0`, so the modulo-WRITE_BUFFER_MAX_SIZE
check at the top of commit_changes() returns early and the explicit
NRF_RRAMC_TASK_COMMIT_WRITEBUF is never triggered.
For sub-buffer writes (e.g. flash_write of 32 B with a 512 B buffer)
the partially-filled write buffer is then only flushed by the
READYNEXTTIMEOUT auto-commit (~4 us), which means data is not yet in
physical RRAM when the API returns. That breaks callers that rely on
write persistence on return.
Capture the original `addr` and `len` once before the throttling loop
mutates them and pass those values to commit_changes(), matching the
behaviour the non-throttled path always had.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Replace hardcoded NUM_DMA_BLOCKS define with Kconfig options
CONFIG_I2S_MCUX_FLEXCOMM_DMA_RX_BLOCKS and
CONFIG_I2S_MCUX_FLEXCOMM_DMA_TX_BLOCKS to allow runtime configuration
of DMA block counts for RX and TX transfers.
Refactor i2s_mcux_config_dma_blocks() to use a loop-based approach
instead of duplicated code blocks, making it more maintainable and
scalable with configurable block counts.
Align the RX start free-buffer check with the configured number of DMA
blocks so the requirement scales with
CONFIG_I2S_MCUX_FLEXCOMM_DMA_RX_BLOCKS instead of assuming two blocks.
Signed-off-by: Michal Chvatal <michal.chvatal@nxp.com>
Reformat i2s_mcux_flexcomm.c to improve code consistency and
readability.
Additionally address static analysis findings on the touched code:
add a default case to the master/slave configuration switch, mirroring
the data format switch, and reduce the cognitive complexity of
i2s_mcux_trigger() by moving the START trigger handling into a dedicated
i2s_mcux_trigger_start() helper.
Signed-off-by: Michal Chvatal <michal.chvatal@nxp.com>
Remove the legacy MDIO and PHY support for the GEM MAC which
dates back to 2021 and doesn't use the MDIO/PHY frameworks
provided by Zephyr nowadays, as those didn't exist back then.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Remove all data/functions/function calls relating to the now
removed legacy MDIO/PHY support directly integrated into the
GEM device driver. Switch over to using the standard MDIO/PHY
interfaces which will now refer to the new separate MDIO
driver and the separated PHY drivers.
Consistently update the qemu_cortex_a9 board definition with
the matching MDIO and PHY nodes, qemu_cortex_a9 is currently
the only Zynq-based target where an enabled GEM instance is
specified by default.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Separate the MDIO functionality from the Xilinx GEM MAC driver
into a separate driver conforming with the standard MDIO API.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Address MISRA integer essential-type findings in the LOAPIC and HPET
paths by making bitmask constants explicitly unsigned and by using
width-safe shifts/casts in register programming code.
The changes are mechanical and preserve behavior while avoiding signed
intermediate expressions in operations that feed uint32_t register
writes.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The data-phase timing comment conflated the controller-measured
transmitter delay (TDC) with the fixed offset (TDCO). Clarify that
only the TDCO is configured via ssp_offset, in time quanta.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Acquire the SDMMC source clock with esp_clk_tree_enable_src() before
selecting it, so the host has a clock even when the ROM left that
reference-clock gate disabled.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
sdmmc_host_set_clk_div() enabled the sample clocks via
sdmmc_ll_init_phase_delay() but never programmed the data-in sampling
phase. On SoCs where that register powers up with a value that does not
sample the data lines correctly, reads return a 0x55/0xAA pattern, the
SCR decodes wrong and the card stays in 1-bit default speed where data
transfers fail. Program the nominal phase 0 after init so reads sample
correctly and high-speed/4-bit negotiation succeeds.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The command dispatch had no entries for the SD erase sequence, so
CMD32 returned -ENOTSUP and any erase request failed. Add the three
erase opcodes: CMD32 and CMD33 as addressed commands with an R1
response, and CMD38 with R1b plus SCF_WAIT_BUSY so the driver waits
for the card to finish erasing before returning.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Update the name of the version register to match the naming convention
used for other registers in the driver and locate based on its address.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
This assigns the device pointer used for the timer during compile time
instead of assigining it at runtime during initialization. This prevents
overwriting the exception vector on Cortex-R5 cores, if a timer is used
before the kernel initialization finished.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
It is possible that TISCI is enabled but the required mailboxes are
not usable due to the mailbox driver being disabled. To provide a more
understandable build error in such cases, BUILD_ASSERT calls have been
added.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
Add the missing open drain support for the families that support it.
Tested with the zephyr,1w-gpio driver on kinetis k66
Signed-off-by: Karl Palsson <karl.palsson@marel.com>
Add a CAN driver for the Espressif TWAI-FD controller used on the
ESP32-C5. The driver implements the full can_driver_api,
supporting Classic CAN and CAN-FD frames.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add support for LPC84x IAP Flash driver to soc_flash_lpc84x_iap.c
Signed-off-by: Dilip Raman <dilipr@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Add UART driver support for NXP LPC84x series.
The driver supports polling and interrupt-driven modes with
runtime configuration. It integrates with Zephyr clock control
and pinctrl for device setup.
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Dilip Raman <dilipr@aerlync.com>
-Added pinctrl driver for the NXP LPC84x series.
-The driver manages pin configuration via the IOCON
peripheral and dynamic pin function assignment via
the Switch Matrix (SWM).
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Dilip Raman <dilipr@aerlync.com>
