- Add clock control driver implementation for the NXP LPC84x series.
- The driver provides system clock initialization, FRO configuration.
Signed-off-by: Deepika R <deepika@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Dilip Raman <dilipr@aerlync.com>
- Enables the digital input buffer for both input and
output pins so the pin level can always be read back.
- Aligns the RT700 GPIO driver with the rest of NXP GPIO
drivers' behavior.
- The read-back is required by self-test routines.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
airoc_wifi_host_buffer_get() returns WHD_BUFFER_ALLOC_FAIL when
net_buf_alloc_len() yields a buffer smaller than the requested size, but
it does so without releasing that buffer, leaking it from the fixed
airoc_pool. Release the undersized buffer with net_buf_unref() before
returning the failure.
Found while characterizing airoc_pool exhaustion under sustained traffic
on rpi_pico2/rp2350a/m33/w (CYW43439). Build- and runtime-tested on that
board: WiFi associate + DHCP + sustained ping with no pool exhaustion
from this path.
Assisted-by: Claude Opus 4.8 <noreply@anthropic.com>
Signed-off-by: Jonathan Beri <jmberi@gmail.com>
When a SPI device uses a GPIO chip select, spi_mcux_configure() initialises
the controller on ECSPI channel 0. However spi_mcux_transfer_next_packet()
started every transfer on transfer.channel = ctx->config->slave.
A device with reg != 0 transfers on an ECSPI channel that was never
configured.
Select the transfer channel the same way spi_mcux_configure() already does:
channel 0 when the chip select is a GPIO, and the slave number only for
native chip selects.
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
Configure and attach the STM clock in the MC_CGM clock init
path when the STM peripheral is used either by the counter
driver or as the Zephyr system timer.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Add an MCUX STM system timer driver selected through the existing
nxp,stm devicetree node referenced by zephyr,system-timer. The driver
uses the free-running STM counter and channel 0 absolute compare to
implement tickful and tickless sys_clock hooks.
The counter clock is derived at runtime from the STM clock-control
provider and the node prescaler, avoiding a second devicetree
clock-frequency source. The deadline math follows the same
last_elapsed model used by the ARM architectural and RISC-V machine
timer drivers, and uses sys_clock_announce_locked() so the kernel
clock lock is shared.
STM compare channels assert only when CNT matches CMP, so compare
programming uses a read-back/retry loop to ensure the programmed value
is genuinely ahead of the current counter and cannot be missed until
32-bit wraparound.
The STM counter driver skips the instance selected as the system timer,
so enabling both drivers does not reinitialize the same hardware.
Validated with west build -p always -b frdm_mcxe31b
zephyr/tests/kernel/timer/timer_behavior and strict UART capture on
FRDM-MCXE31B; all timer_behavior suites passed. Also built the same
test with CONFIG_COUNTER_MCUX_STM=y to cover the skipped counter
instance path.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The main goal of this change is being able to use counter_gecko_rtcc.c and
leuart_gecko.c on boards without an LFXO. This is the case for tyzs3.
The main changes are in soc/silabs/common, the rest is just to migrate all
of the boards.
This uses the device tree for clock-initialization only. I did not
implement a clock_control driver, because I don't see a need for that. The
drivers use CMU_ClockEnable, which abstracts away SoC differences already.
The config SOC_GECKO_HAS_HFRCO_FREQRANGE was removed, because:
- This can be detected via macros provided by gecko_sdk.
- There is an alternative to that API which wasn't implemented previously,
but is now (cmuHFRCOBand_*).
I don't own any of the boards except for tuya tyzs3, but did my best to
avoid mistakes. That being said, I found several issues, which were present
in some of the boards already:
- sltb004a: This board has a 38.4MHz HFXO crystal, but it was configured to
40MHz. I fixed that.
- tomu: This board uses HFRCO as it's HF clock, even though the SoC does
not support SOC_GECKO_HAS_HFRCO_FREQRANGE. So it was probably running at
the initial 14MHz instead.
- Many boards enabled leuart and rtcc (counter) peripherals, which need(ed)
LFXO, without ever enabling LFXO. These peripherals were probably not
working before this change.
Noteworthy finds:
- slwrb4321a: This board uses HFRCO as it's HF clock, but has a board.c
where it enables HFXO to use it as the RMII reference clock. I'm not sure
if it's okay to do that without calling CMU_HFXOInit first. I did not
modify that code to not change behavior that I don't understand.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
Mesh uses legacy packets with extended advertiser.
Dropping of ext adv events is normal behavior.
However, mesh samples ara spammed these error messages
on some platforms.
Signed-off-by: Aleksandr Khromykh <aleksandr.khromykh@nordicsemi.no>
Remove the deprecated counter-based Maxim DS3231 driver and its
dedicated API, binding, sample, and test coverage.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add a bad block cache by keeping a bad block table in memory.
This will speed up bad block checking at the cost of slightly
increased memory usage of 1 bit per erase block.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
For PTP clocks which are explicitly part of Ethernet device
to provide PTP timestamping. We can select NET_L2_PTP_TIMESTAMPING
to provide Ethernet device driver complete dependency for PTP
timestamping support.
User doesn't have to take care of NET_L2_PTP_TIMESTAMPING enablement
in other places, and Ethernet device driver can control PTP
timestamping enablement via its PTP clock Kconfig option.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
For PTP clocks which are explicitly part of Ethernet device
to provide PTP timestamping. We can select NET_L2_PTP_TIMESTAMPING
to provide Ethernet device driver complete dependency for PTP
timestamping support.
User doesn't have to take care of NET_L2_PTP_TIMESTAMPING enablement
in other places, and Ethernet device driver can control PTP
timestamping enablement via its PTP clock Kconfig option.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Renamed NET_L2_PTP Kconfig option to NET_L2_PTP_TIMESTAMPING,
to make its function clear to user. Also made it depend on
PTP_CLOCK which was more reasonable.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
save rx_pkt and bytes, like in the qos mac, in case
we got already got fragments of later packets.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Generic MSPI driver for the ISSI IS66/67WV Serial PSRAM family
(both wrapped-burst WVS and continuous WVR variants).
Implements MEMC read/write for bus-transaction access via MSPI.
When CONFIG_MSPI_XIP=y and xip-config is present in DT with
enable=true, also implements get_mem_base so the memcpy path
is used automatically on controllers with a memory-mapped
aperture.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
Macro DT_INST_SCMI_PROTOCOL_DEFINE() requires 10 arguments,
but only 9 were given. This patch adds the missing one.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Disable Wake-Up Timer before setting a new compare value to comply with
user guide recommendations.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
The March-2026 Ethernet API migration (commit db984ee196) added
struct net_if *iface to the net_if_api start/stop declarations but
the eth_xlnx_gem_start_device and eth_xlnx_gem_stop_device definitions
were not updated, causing a build failure for any target that enables
the GEM driver (e.g. Zynq-7000 with zperf).
Add the missing parameter to both definitions.
Signed-off-by: Iustin Stolniceanu <iustin.stolniceanu@analog.com>
Add explicit JEDEC handling for the ISSI IS25LP512M. Configure the
FlexSPI LUT for 4-byte Quad I/O reads plus 4-byte page program, sector
erase, and block erase commands.
The IS25LP512M uses nonvolatile SR1 bit 6 as the QE bit, so enable quad
mode with the existing S1B6 helper before using the 1-4-4 read path.
Hardware was verified by clearing SR1 QE from 0x40 to 0x00, setting it
back to 0x40, and passing quad erase/program/readback.
Fixes#111686
Signed-off-by: Eli Hughes <eli.hughes@nxp.com>
Change calibration process to handle differential calibration
Configure channel 10 to differential for Nucleo N657X0-Q and
STM32N6570-DK in `adc_api` test
Pin PA10 (Arduino A2) is shared as positive input for channel 11
and negative input for channel 10, allowing to keep default pin
configuration to test single and differential input.
Signed-off-by: Basile GRUNER <basile.gruner@smile.fr>
This is a follow-up to commit d7d1a64e27.
The above commit added `MSPI_DEVICE_CONFIG_IO_MODE` to `XIP_DEV_CFG_MASK`,
but in consequence it removed that bit from `NON_XIP_DEV_CFG_MASK` since
the latter is defined with `& ~XIP_DEV_CFG_MASK`. And that bit must be
present in `NON_XIP_DEV_CFG_MASK`, otherwise the driver will not configure
IO mode as expected in `switch_to_target_io_mode()` and `_acquire()`.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This reverts commit 97bfea46a0.
Contrary to what the above commit description says, the change it brings
does not in fact cause IO mode to be switched in the MSPI controller.
That is because `switch_to_target_io_mode()` uses `NON_XIP_DEV_CFG_MASK`
in its call to `mspi_dev_config()` and after recent changes (see commit
d7d1a64e27) that mask does not actually
include the `MSPI_DEVICE_CONFIG_IO_MODE` bit.
Revert the commit as it unnecessarily doubles the operations related to
switching the flash chip to desired IO mode (like the `post_switch_mode`
quirk), without fixing the actual problem with IO mode incorrectly set
in the MSPI controller.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add a GPIO expander driver for the Raspberry Pi BCM283x, using
the VideoCore firmware property interface.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add support for output open drain mode which is used by the tests in
`tests/drivers/gpio/gpio_basic_api/`.
While there, switch some magic numbers to the corresponding HAL
defines and be stricter on invalid or unsupported configurations.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Forward rtc_set_calibration() and rtc_get_calibration to the underlying
counter device via counter_set_calibration and
counter_get_calibration().
Both APIs use parts per billion (ppb), so no conversion is needed.
Translate -ENOSYS from the counter layer to -ENOTSUP to preserve the
error code documented by the RTC API.
Select COUNTER_CALIBRATION from Kconfig when RTC_CALIBRATION is enabled
to ensure the counter calibration API is compiled in.
Signed-off-by: Harini T <harini.t@amd.com>
Allow rtc_counter_set_time() to proceed when counter_stop() or
counter_start() returns -ENOTSUP. Both APIs may return -ENOTSUP for
always-on counters that cannot be stopped or started. Without this,
rtc_set_time() fails unconditionally on such hardware.
Signed-off-by: Harini T <harini.t@amd.com>
Set the counter tick value directly in hardware via counter_set_value()
instead of relying solely on a software offset.
Fall back to the existing software offset when the counter does not
implement set_value or the desired tick value exceeds 32 bits.
Signed-off-by: Harini T <harini.t@amd.com>
Add nor flash drivers for Realtek Bee family SoCs (RTL8752H and RTL87x2G).
Supports read, write, erase operations with page layout support.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Implement device runtime power management for the SiWx91x
entropy driver. This ensures that the RNG is automatically
reenabled after deep sleep.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Check that the buffer length is a multiple of the data size, and return
an error if it's not the case.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Do not store stack-allocated pointers in the SPI data structure.
Set current_tx and current_rx to NULL since they are not used in RTIO
anyway.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Adapt the STM32 SPI driver so that in RTIO, transactions can be done either
in interrupt or in DMA mode, for different instances (until now, once
CONFIG_SPI_STM32_DMA was enabled, all transactions had to be done with
DMA).
Also use the asynchronous DMA callback for RTIO since it shares a lot of
code.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The transceive and transceive_dma functions had some similar code.
Factorize them to reduce code duplication. transceive_dma is now called
from the transceive function, and only the latter is called from the
.transceive and .transceive_async API functions.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit fixes issues that could arise notably when only the slave was
sending data (and the master was only receiving). By keeping track of bytes
transmitted in both directions (the context may not keep track of a
direction if the associated buffer is NULL or the length is 0), we prevent
the master side to abort the transmission prematurely.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fixes the slave mode for st,stm32h7-spi compatibles by setting the
transfer size also for the slave device, and also waiting for SPI to not be
busy before calling the "complete" function (or else the transaction might
end too early in case where only the slave sends data).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
CONNECT_CMUX had no handler for CMUX_DISCONNECTED, so a modem that never
establishes CMUX (left in an unknown state, for example a wrong baud
rate after an interrupted firmware update) stalled the driver in
CONNECT_CMUX with no way out.
Route CMUX_DISCONNECTED through modem_cellular_enter_recovery_state(),
the same recovery the init script uses, pulsing the reset line when one
is present and enabled to return the modem to a known state.
Signed-off-by: Paulo Santos <pauloxrms@gmail.com>
The init-script failure path picks between a reset pulse, a power pulse
and idle based on which control GPIOs the board wires and the
reset_on_recovery setting. Factor that selection into
modem_cellular_enter_recovery_state() so other failure paths reuse it
without duplicating the GPIO gating.
Signed-off-by: Paulo Santos <pauloxrms@gmail.com>
This change adds basic target mode support for STM32 products.
Controller writes to target, and reading from the target, is supported.
Signed-off-by: James Growden <jgrowden@tenstorrent.com>
Add a counter driver for the Xilinx Zynq Ultrascale+ MPSoC Real Time
Clock. The hardware provides a 32-bit seconds counter driven by an
external crystal oscillator, one alarm channel, and a calibration
register with integer and fractional tick adjustment.
The driver implements the Zephyr counter API and is intended to be used
with the rtc_counter wrapper to expose the standard RTC API.
The RTC oscillator runs continuously so start() and stop() return
-ENOTSUP. Calibration support is gated by CONFIG_COUNTER_CALIBRATION.
Signed-off-by: Harini T <harini.t@amd.com>
Add optional set_calibration/get_calibration operations to the counter
driver API. Calibration is specified in parts per billion (ppb). The
operations are gated behind CONFIG_COUNTER_CALIBRATION and return
-ENOSYS if not implemented by the driver.
Signed-off-by: Harini T <harini.t@amd.com>
